參數(shù)資料
型號(hào): S5D2510
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: stand-alone OSD Processor
中文描述: 獨(dú)立OSD處理器
文件頁數(shù): 2/32頁
文件大?。?/td> 267K
代理商: S5D2510
S5D2510
OSD PROCESSOR FOR MONITOR (PRELIMINARY)
2
BLOCK DIAGRAM
The OSD Processor consists of 8 blocks on the top level as shown "Figure 1: Functional block diagram".
There are 4 input signals for the OSD Processor, which are serial data (SDA), clock (SCL) form a micro controller
and sync signals (HFLB and VFLB) from the H/ V sync processor. Through the serial data line, all information for
the OSD operation are transferred. Here, the protocol is I
2
C bus.
The data receiver block is a decoder for decoding the serial input data from a micro controller. The serial data is
converted to a 16-bit parallel format at the data receiver block. The parallel data are transported to the RAM or
registers by the bus line. The internal bus is a kind of star-bus type.
Control data comes from the data receiver is used to generate the control signals that control the character size,
character position, blank mode, blink mode, background color, and etc, in timing controller and display unit block.
All timing signals to read/ write data from/ to the internal RAM and ROM are also generated in the timing
controller block. In the PLL block, the internal system clock that is synchronized with HFLB is generated, which is
used as a timing reference signal for the OSD processor.
/
/
/
/
9
6
8
7
15
14
13
12
11
2
3
4
16
10
5
1
OSD PLL
C
Data Receiver
(IIC Controller)
Timing
Controller
Output Stage
Display
Controller
Display RAM
(1K-Byte SRAM)
Multi
Color
ROM
(16X3X18X12)
Single
Color
ROM
(448X18X12)
/
V
V
V
VFLB
HFLB
SCL
SDA
INT
R_OUT
G_OUT
B_OUT
FBLK
V
V
V
V
V-Pulse
H-Pulse
CLK
Control
Data
RAM
Data
ROM
Address
Font
Data
Font
Data
Font
Control
Frame
Control
Row
Control
Frame
Control
Row
Control
H/V/CLK
Control
H/V/CLK
Control
Display
Control
16
16
9
12
12
Figure 1. Functional Block Diagram
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