參數(shù)資料
型號(hào)： S5D2510
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： stand-alone OSD Processor
中文描述： 獨(dú)立OSD處理器
文件頁數(shù)： 29/32頁
文件大小： 267K
代理商： S5D2510
OSD PRESSOR FOR MONITOR (PRELIMINARY)
S5D2510
29
PLL CONTROL
PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a
reference signal and an oscillator output signal. The PLL of S5D2510 is charge-pump PLL , and is generally
composed PFD, charge pump, VCO, and Divider.
To support VGA
UXGA grade, divider has the ratio of 640/ 800/ 1024/ 1280, and the range of the HFLB input
frequency for reference is 30kHz
120kHz. At this time, needed the output frequency of VCO is 19.2 MHz
153.6MHz.
H/ W and S/ W setting is needed for optimal operation of PLL. The application circuit of Pin #2 and Pin #3 is
representative of H/ W setting. CP, FHF, and DOT bits in "Frame Control Register 1" is representative of S/ W
setting.
You had better set the tuning factor explained above by referring to the following reference.
Locking Range
As you can see the figure below, it is 2.5V that measured voltage at Pin #2 to optimize OSD quality. Also, locking
voltage range of PLL is 1.0V
4.0V, and the proper voltage range of PLL to capture well is 1.7V
3.3V.
fL (Locking)
fC (Capture)
fO
1.0V
1.7V
2.5V
3.3V
4.0V
fMax
Ve(max)
Ve(min)
1.5V
1.5V
Figure 21 : PLL Locking Range
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