- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368612 > S5L9276X01 (SAMSUNG SEMICONDUCTOR CO. LTD.) OPTICAL CD MP3 SYSTEM PDF資料下載
參數(shù)資料
| 型號(hào)： | S5L9276X01 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 通用總線功能 |
| 英文描述： | OPTICAL CD MP3 SYSTEM |
| 中文描述： | 光學(xué)CD MP3播放系統(tǒng) |
| 文件頁(yè)數(shù)： | 26/50頁(yè) |
| 文件大?。?/td> | 182K |
| 代理商： | S5L9276X01 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)
S5L9276 (PRELIMINARY SPEC)
OPTICAL CD MP3 SYSTEM
26
Registers for configuration of clock
// Read only registers (8'h40
8'h4F reserved for ckgUnit - Read)
// Write only registers (8'hD0
8'hDF reserved for ckgUnit)
H_PLL0_P0
H_PLL0_M0
H_PLL0_S0
H_PLL1_P1
H_PLL1_M1
H_PLL1_S1
H_CKG_DIV_XY
H_CKG_CMD_0
H_SLEEP_CR
8'hd0
8'hd1
8'hd2
8'hd3
8'hd4
8'hd5
8'hd6
8'hd7
8'hdf
P register for PLL0 (See chapter 7.)
M register for PLL0 (See chapter 7.))
S register for PLL0 (See chapter 7.))
P register for PLL1 (See chapter 7.))
M register for PLL1 (See chapter 7.))
S register for PLL1 (See chapter 7.))
(See chapter 7.))
(See chapter 7.))
SLEEP control register
bit7
1 : don't care
bit0 :
If "1", Set S5L9276 to SLEEP mode.
If "0", set S5L9276 to RUNNING mode.
Registers for reset control
// Write only registers (8'hE0
8'hEF reserved for rstUnit - Write)
H_SOFT_RST
8'hE0
Master reset by software control
Registers for DRAM access and Interrupt Source Register
// Read only registers (8'h50
8'h5F reserved for hifUnit - Read)
H_MEM_READ
H_INT_READ
8'h50
8'h51
Buffer Register for DRAM burst read
Interrupt Source Register
// Write only registers (8'hF0
8'hFF reserved for hifUnit - Write)
H_MEM_ADDR_HIGH
H_MEM_ADDR_MID
H_MEM_ADDR_LOW
H_MEM_ADDR_BL
H_MEM_WRITE
H_MEM_WRITE_IB
8'hf0
8'hf1
8'hf2
8'hf3
8'hf4
8'hf5
High byte of start address for DRAM burst read
Middle byte of start address for DRAM burst read
High byte of start address for DRAM burst read
Burst Length for DRAM burst read (1
63, default is 1.)
Buffer Register for DRAM burst write
Buffer Register for Input Buffer in DRAM burst write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5L9284 | DIGITAL SIGNAL PROCESSOR |
| S5L9284D01-Q0R0 | IC, 10/100BASE-TX DUAL-PORT DIGI-PHY TRANSCEIVER, QFP14 |
| S5L9284D | DIGITAL SIGNAL PROCESSOR |
| S5L9286F02 | DIGITAL SIGNAL PROCESSOR |
| S5L9286F02-T0R0 | DIGITAL SIGNAL PROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5L9284 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR |
| S5L9284D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR |
| S5L9284D01-Q0R0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR |
| S5L9286 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR FOR CDP |
| S5L9286F01-Q0R0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR FOR CDP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。