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參數(shù)資料
| 型號(hào)： | S71PL032JA0BFW0F4 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁(yè)數(shù)： | 160/188頁(yè) |
| 文件大?。?/td> | 5078K |
| 代理商： | S71PL032JA0BFW0F4 |
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72
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127_064_032J_00_A1 May 21, 2004
Prelimin ary
Table 18. Sector Protection Command Definitions
Command (Notes)
Cy
cl
e
s
Bus Cycles (Notes 1-4)
Addr Data Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
1
XXX
F0
SecSi Sector Entry
3
555
AA
2AA
55
555
88
SecSi Sector Exit
4
555
AA
2AA
55
555
90
XX
00
SecSi Protection Bit
6
555
AA
2AA
55
555
60
OW
68
OW
48
OW
RD(0)
SecSi Protection Bit
Status
5
555
AA
2AA
55
555
60
OW
48
OW
RD(0)
Password Program
(Notes 5, 7, 8)
4
555
AA
2AA
55
555
38
XX[0-3]
PD[0-3]
Password Verify (Notes
4
555
AA
2AA
55
555
C8
PWA[0-3] PWD[0-3]
Password Unlock (Notes
7
555
AA
2AA
55
555
28
PWA[0]
PWD[0]
PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3]
PPB Program (Notes 5,
6
555
AA
2AA
55
555
60
(SA)WP
68
(SA)WP
48
(SA)WP
RD(0)
PPB Status
4
555
AA
2AA
55
555
90
(SA)WP
RD(0)
All PPB Erase (Notes 5,
6
555
AA
2AA
55
555
60
WP
60
(SA)
40
(SA)WP
RD(0)
PPB Lock Bit Set
3
555
AA
2AA
55
555
78
PPB Lock Bit Status
4
555
AA
2AA
55
555
58
SA
RD(1)
DYB Write (Note 7)
4
555
AA
2AA
55
555
48
SA
X1
DYB Erase (Note 7)
4
555
AA
2AA
55
555
48
SA
X0
DYB Status (Note 6)
4
555
AA
2AA
55
555
58
SA
RD(0)
PPMLB Program (Notes
6
555
AA
2AA
55
555
60
PL
68
PL
48
PL
RD(0)
PPMLB Status (Note 5)
5
555
AA
2AA
55
555
60
PL
48
PL
RD(0)
SPMLB Program (Notes
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
RD(0)
SPMLB Status (Note 5)
5
555
AA
2AA
55
555
60
SL
48
SL
RD(0)
Legend:
BA = Address of bank switching to autoselect mode, bypass
mode, or erase operation. Determined by PL127J: Amax:A20,
PL064J: Amax:A19, PL032J: Amax:A18.
PA = Program Address (Amax:A0). Addresses latch on falling
edge of WE# or CE# pulse, whichever happens later.
PD = Program Data (DQ15:DQ0) written to location PA. Data
latches on rising edge of WE# or CE# pulse, whichever happens
first.
RA = Read Address (Amax:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (Amax:A12) for verifying (in autoselect
mode) or erasing.
WD = Write Data. See “Configuration Register” definition for
specific write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
write operations.
4. During unlock and command cycles, when lower address bits
are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than
DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading
array data.
6. The Reset command is required to return to reading array
(or to erase-suspend-read mode if previously in Erase
Suspend) when bank is in autoselect mode, or if DQ5 goes
high (while bank is providing status information).
7. Fourth cycle of autoselect command sequence is a read
cycle. System must provide bank address to obtain
manufacturer ID or device ID information. See Autoselect
Command Sequence section for more information.
8. The data is C0h for factory and customer locked and 80h for
factory locked.
9. The data is 00h for an unprotected sector group and 01h for
a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. PL127J
(X0Eh = 2220h, X0Fh = 2200h),PL064J (X0Eh = 2202h,
X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h).
11. System may read and program in non-erasing sectors, or
enter autoselect mode, when in Program/Erase Suspend
mode. Program/Erase Suspend command is valid only
during a sector erase operation, and requires bank address.
12. Program/Erase Resume command is valid only during Erase
Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or
when device is in autoselect mode.
14. WP#/ACC must be at VID during the entire operation of
command.
15. Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. Unlock Bypass Reset command is
required to return to the reading array.
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