參數(shù)資料
型號: SAA2023
廠商: NXP Semiconductors N.V.
英文描述: Drive processor for DCC systems
中文描述: 戴納信貸驅(qū)動處理器的系統(tǒng)
文件頁數(shù): 35/56頁
文件大?。?/td> 274K
代理商: SAA2023
May 1994
35
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
Table 32
T1F2 to T1F0 CHTST1 pin function selections.
The digital eye pattern is in 8 bits two’s complement notation, the sliced data and the bit clock give the current binary
state of the corresponding signals, and the clock extraction frequency output is in 8 bits offset binary format. The timing
diagrams for the digital eye pattern output and the clock extraction frequency output are shown in Fig.29.
T2sel register
Table 33
T2SEL register CHTST2 pin selection register.
T1F
FUNCTION OF CHTST1 PIN
2
1
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
off; logic 0
digital eye pattern
sliced data
bit clock
clock extraction frequency
BIT
7
0
6
5
4
3
2
1
0
Meaning
Default
T2F2
0
T2F1
0
T2F0
0
T2C3
0
T2C2
0
T2C1
0
T2C0
0
Table 34
T2C3 to T2C0 CHTST2 pin channel selections.
T2C
CHANNEL ON
CHTST2
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
AUX
Table 35
T2F2 to T2F0 CHTST2 pin function selections.
T2F
FUNCTION OF CHTST2 PIN
2
1
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
off; logic 0
digital eye pattern
sliced data
bit clock
clock extraction frequency
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