參數(shù)資料
型號(hào): SAA2023
廠商: NXP Semiconductors N.V.
英文描述: Drive processor for DCC systems
中文描述: 戴納信貸驅(qū)動(dòng)處理器的系統(tǒng)
文件頁數(shù): 47/56頁
文件大?。?/td> 274K
代理商: SAA2023
May 1994
47
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
Clock output MCLK
C
L
t
d
load capacitance
delay time from SLEEP HIGH to
SLEEP active
clock frequency
MCLK pulse width LOW
MCLK pulse width HIGH
propagation delay time from rising
edge of CLK24
20
20
pF
ns
f
MCLK
t
MCL
t
MCH
t
pd
6.144
6.25
65
MHz
ns
ns
ns
50
50
Inputs
C
I
L3CLK, L3MODE
AND
RESET
input capacitance
10
pF
t
su
t
h
PINI
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
35
0
ns
ns
t
su
t
h
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
60
0
ns
ns
Outputs
C
L
A0
TO
A8
load capacitance
20
pF
t
pd
propagation delay time from falling
edge of CLK24
50
ns
A9/CAS, A10/RAS
AND
OEN
t
pd
propagation delay time from falling
edge of CLK24
delay time from SLEEP HIGH to
SLEEP active
50
ns
t
d
20
ns
WEN
t
pd
propagation delay time
from falling edge of CLK24
from falling edge of WEN to rising
edge of CLK24
delay time from SLEEP HIGH to
SLEEP active
50
50
ns
ns
long write pulse
mode
t
d
20
ns
AZCHK, CHTST1, CHTST2, L3INT, PINO3, RDSYNC, SBEF
AND
WDATA
t
pd
propagation delay time from rising
edge of MCLK
45
ns
ERCOSTAT, L3REF, SBDIR, SPEED, PINO2, URDA
AND
TCLOK
t
pd
propagation delay time from rising
edge of MCLK
55
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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