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參數(shù)資料
| 型號(hào)： | SAA4951 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | RES 6.49K OHM 1/16W 0.5% 0402SMD |
| 中文描述： | 內(nèi)存控制器 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大小： | 95K |
| 代理商： | SAA4951 |
April 1994
16
Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
BLND
The output signal BLND is a horizontal blanking pulse and
is used for the peripheral circuits NORIC and BENDIC.
A LOW level indicates the blanking interval, a HIGH level
indicates valid data from the memories. It is possible to
delay the horizontal timing of BLND up to three steps of
LLD clock pulses.
WE2
A HIGH level on this output pin enables picture data to be
written to field memory 2. WE2 is a composite signal,
which includes the horizontal write enable signal as well as
the vertical one.
The horizontal timing of WE2 can be delayed up to three
steps of LLD clock pulses.
The WE2 output signal is used in different modes. When
two field memories are implemented in a serial structure,
WE2 operates at a vertical frequency of 100 Hz. In case
two field memories are connected in parallel, WE2 has a
vertical frequency of 50 Hz. In the progressive scan mode
the WE2 signal is disabled every second field.
Table 6
Horizontal programming range for display signals (HDSP = BLN, WE2, RE1 or RE2; see also Fig.8).
Nr
≠
Nf
27 MHz, 50 Hz
HDSP
r
= (2Nr
+
2)
×
LLD
HDSP
f
= (2Nf
+
2)
×
LLD
HDSP
r
= (2Nr
+
2)
×
LLD
HDSP
f
= (2Nf
+
2)
×
LLD
HDSP
r
= (2Nr
+
2)
×
LLD
HDSP
f
= (2Nf
+
2)
×
LLD
HDSP
r
= (4Nr
+
4)
×
LLD
HDSP
f
= (4Nf
+
4)
×
LLD
HDSP
r
= (4Nr
+
4)
×
LLD
HDSP
f
= (4Nf
+
4)
×
LLD
0
≤
Nr
<
431
0
<
Nf
≤
431
0
≤
Nr
<
428
0
<
Nf
≤
428
0
≤
Nr
<
511
0
<
Nf
≤
511
0
≤
Nr
<
287
0
<
Nf
≤
287
0
≤
Nr
<
285
0
<
Nf
≤
285
27 MHz, 60 Hz
32 MHz
36 MHz, 50 Hz
36 MHz, 60 Hz
Fig.8 Programmable horizontal display signals (HDSP = BLN, WE2, RE1 or RE2).
handbook, full pagewidth
HRD
MGH137
HDSP
HDSPr
HDSPf
IE2
This output signal is used as data input enable for
memory 2. A logic HIGH level on this output pin enables
the data information to be written to field memory 2.
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| SAA4951WP | Memory controller |
| SAA4952WP | Memory controller |
| SAA4955 | 2.9-Mbit field memory |
| SAA4955TJ | 2.9-Mbit field memory |
| SAA4956TJ | 2.9-Mbit field memory with noise reduction |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4951WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4952WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller |
| SAA4955 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
| SAA4955TJ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
| SAA4956TJ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory with noise reduction |
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