參數(shù)資料
型號(hào)： SAA4951
廠商： NXP Semiconductors N.V.
英文描述： RES 6.49K OHM 1/16W 0.5% 0402SMD
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 18/25頁(yè)
文件大小： 95K
代理商： SAA4951
April 1994
18
Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
Description of deflection part
LLDFL
The input signal LLDFL is the main line-locked clock pulse
for the deflection side of the memory controller generated
by an external PLL circuit. The frequency of LLDFL is
always 27 MHz and is independent of the chosen feature
modes. The PLL circuit operates on the video clamping
pulse CLV of the acquisition part and the horizontal
reference signal HRDFL generated by the deflection side
of SAA4951.
HRDFL
This horizontal output signal is the reference pulse for the
horizontal deflection drive signal HDFL. The duty cycle of
HRDFL is 50% and the cycle time is 64
μ
s (PAL). In case
of golden scart mode the cycle time is reduced to 32
μ
s.
HDFL
The output signal HDFL is aimed for driving the connected
horizontal deflection circuit. HDFL has a cycle time of
32
μ
s and a pulse width of 64 x LLDFL = 2.37
μ
s
Fig.10 Horizontal deflection timing.
handbook, full pagewidth
MGH139
HRDFL
HDFL
64
×
LLDFL
64
×
LLDFL
864/858
×
LLDFL (50/60 Hz)
432/429
×
LLDFL (50/60 Hz)
VDFL
This is the vertical synchronization output signal generated
by the acquisition side of SAA4951. The timing reference
of VDFL is the LOW-to HIGH transition of the vertical
acquisition input pulse VACQ. Normally VDFL has a pulse
width of 2.5 x HDFL = 80
μ
s and a cycle time of 100 Hz.
In normal mode the memory controller operates with two
field memories and 100 Hz interlace picture reproduction.
When the system includes only one field memory it is
necessary to activate the AABB mode. In the simple field
repetition mode the first two and the last two 100 Hz fields
are out one upon another
Description of control inputs/outputs
ALE
The address latch enable input signal ALE is provided by
the microcontroller. A falling edge of ALE denotes a valid
address.
WRD
This is the write/read enable control signal supplied by the
microcontroller. The HIGH-to-LOW transition of WRD
indicates valid data.
P0 to P7
The SAA4951 is controlled by the bidirectional port bus
P0.0 to P0.7 of a microcontroller. Address and data are
transmitted sequentially on the bus.
TEST
The TEST input pin has to be connected to ground.
相關(guān)PDF資料
PDF描述
SAA4951WP Memory controller
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SAA4955TJ 2.9-Mbit field memory
SAA4956TJ 2.9-Mbit field memory with noise reduction
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA4951WP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller
SAA4952WP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Memory controller
SAA4955 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory
SAA4955TJ 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory
SAA4956TJ 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory with noise reduction
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