參數(shù)資料
型號: SAA4951
廠商: NXP Semiconductors N.V.
英文描述: RES 6.49K OHM 1/16W 0.5% 0402SMD
中文描述: 內(nèi)存控制器
文件頁數(shù): 17/25頁
文件大?。?/td> 95K
代理商: SAA4951
April 1994
17
Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
RE1
The output RE1 is the read enable signal for field
memory 1. A HIGH level enables the picture data to be
read from the memory. RE1 is a composite signal and
includes the horizontal read enable timing as well as the
vertical timing. It is possible to delay the horizontal timing
of RE1 up to three steps of LLD clock pulses.
Furthermore the vertical timing can be set one or two lines
before RE2 respectively one line after RE2 (median
filtering, noise reduction mode).
RE2
The output RE2 is the read enable signal for field
memory 2. A HIGH level enables the picture data to be
read from memory 2. RE2 is a composite signal and
includes the horizontal read enable timing as well as the
vertical timing. The horizontal timing of RE2 can be
delayed up to three steps of LLD clock pulses.
Table 7
Vertical programming range for display signals (VDSP = WE2, RE1 or RE2; see also Fig.9).
Nr
Nf
50 Hz
VDSP
r
= Nr
×
Line
VDSP
f
= Nf
×
Line
VDSP
r
= Nr
×
Line
VDSP
f
= Nf
×
Line
1
Nr
<
311
1
<
Nf
311
1
Nr
<
261
1
<
Nf
261
60 Hz
Fig.9 Vertical display timing (VDSP = V
WE2
, V
RE1/2
or VDFL).
handbook, full pagewidth
MGH138
VACQ
VDSP
RSTW2
VDSPr
VDSPf
RSTW2
The reset write output pulse 2 starts the write address
pointer of field memory 2. There are two functions possible
for this pin. If a serial structure of the memories is
implemented, RSTW2 is a 100 Hz pulse; in progressive
scan mode and with one field memory, RSTW2 is a 50 Hz
pulse. The pulse duration of RSTW2 is 32
μ
s (PAL).
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