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參數(shù)資料
| 型號： | SAA4978H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Picture Improved Combined Network PICNIC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 296K |
| 代理商： | SAA4978H |
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1999 May 03
16
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
7.3
Analog output blocks
7.3.1
T
RIPLE
10-
BIT DIGITAL
-
TO
-
ANALOG CONVERSION
Three identical DACs are used to convert Y, U and V with
a 32 or 16 MHz data rate.
7.3.2
A
NALOG ANTI
-
ALIASING POST
-
FILTER
A 3rd-order linear phase filter is applied to each of the Y,
U and V channels. It provides a notch on f
clk
(32 MHz at Y,
U and V) to strongly prevent aliasing to low frequencies,
which would be most disturbing. The filters can be
bypassed if external filtering with other characteristics is
desired. Bandwidth and gain accuracy are given in
Chapter 11.
7.3.3
PLL
The PLL consists of a ring oscillator, Discrete Time
Oscillator (DTO) and digital control loop. The PLL
characteristic is controlled by means of the
microcontroller.
7.3.4
SNERT
A SNERT interface is built-in to transform the parallel data
from the microcontroller into 1 or 2 Mbaud switchable
SNERT data. This interface is also capable of reading data
from the SNERT bus should it be required to access read
registers.
The read or write operation must be set by the
microcontroller. When writing to the bus, 2 bytes are
loaded by the microcontroller; one for the address, the
other for the data. When reading from the bus, 1 byte is
loaded by the microcontroller for the address, the received
byte is the data from the addressed SNERT location.
The SNERT interface replaces the standard UART
interface. In contrast to the 80C51 UART interface there
are additional control registers, other I/O pads and no byte
separation time between address and data. After
power-on reset the 1 Mbaud mode is active. Switching
baud rate during transmission should be avoided.
7.3.5
PSP
For dynamically changing data such as timing signals, the
programmable signal positioner generates them on the
basis of parameters sent by the microcontroller. For the
reset function of the microcontroller, a watchdog timer is
also built-in that creates a reset pulse unless it is triggered
by a change in the Bone signal within a preset time
(1.05 s).
7.3.6
M
ICROCONTROLLER
The SAA4978H contains an embedded 80C51
microcontroller core including a 1 kbyte RAM and a
32 kbyte ROM. It also includes an I
2
C-bus user control
interface. For development reasons an external ROM can
be accessed with 64 kbyte maximum size. An external
emulator can be connected.
The main difference to most existing 80C51 derivatives is:
768 byte auxiliary RAM from which 128 bytes can be
accessed as subtitle RAM
Interrupt vector address for the I
2
C-bus is 33H
On-chip ROM code protection
SNERT at 1 or 2 Mbaud with additional Sample
Frequency Registers (SFRs) instead of UART
Host interface containing all control registers access
e.g. via MOVX instruction.
7.3.7
B
OARD LEVEL TESTABILITY
Boundary scan test is implemented, according to
“IEEE standard 1149.1” The boundary scan affects all
digital pins and will cover all connections from the
SAA4978H to other ICs that are also equipped with BST.
The connectivity of the analog YUV input/output pins can
also be tested with the use of BST.
The digital outputs UVAL, UVA0, UVA1, UVA2, UVA3,
YAL, UVCL, UVC0, UVC1, UVC2, UVC3, YCL, WEA,
WEC and IEC can be set in 3-state mode if not connected
in the application. This means that these outputs with
index 0 to 3 are set in 3-state if 4 : 1 : 1 is chosen, and the
outputs with index L are set in 3-state if 8 bits output is
chosen.
7.3.8
P
OWER
-
ON RESET
All digital blocks except PLL are reset by a HIGH level at
the reset pin. Only the watchdog counter is reset by the
falling edge of the reset pulse. The PLL needs no reset.
The frequency guard generates a single reset pulse with a
duration of 0.875 ms when the actual frequency enters the
desired range of 14 to 18 MHz. If the frequency leaves this
range then no reset pulse is generated.
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