參數(shù)資料
型號(hào)： SAA4978H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Picture Improved Combined Network PICNIC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 40/56頁(yè)
文件大?。?/td> 296K
代理商： SAA4978H
1999 May 03
40
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
t
h(o)
SR
output hold time
slew rate
see Fig.4
4
200
500
700
ns
Digital input bus B and D; timing referred to CLK32 for bus D and to CLK16, CLK32 or CLKAS for bus B
(see
Fig.4)
; the reference for bus B depends on the selected mode respectively single clock, double clock or
asynchronous clock
V
IL
V
IH
t
su(i)
t
h(i)
LOW-level input voltage
HIGH-level input voltage
input set-up time
input hold time
0
2.0
6
1
0.8
5.5
V
V
ns
ns
5 V tolerant
see Fig.4
see Fig.4
CLKAS
V
IL
V
IH
t
h(i)(async)
LOW-level input voltage
HIGH-level input voltage
asynchronous input hold
time
minimum LOW time
minimum HIGH time
minimum period time
0
2.0
4
0.8
5.5
V
V
ns
5 V tolerant
t
L(min)
t
H(min)
T
CLKAS(min)
T
CLK32
10
10
ns
ns
ns
the asynchronous clock
may not be faster than
CLK32
CLK16 and CLK32 (C
L
= 30 pF; I
OL
= 2 mA; R
L
= 2 k
)
V
OL
V
OH
t
o(r)
t
o(f)
t
dHO
LOW-level output voltage
HIGH-level output voltage
output rise time
output fall time
CLK16 HIGH transition
delay time
CLK16 HIGH transition
hold time
CLK16 LOW transition
delay time
CLK16 LOW transition
hold time
0
2.4
2
2
3
3
0.4
4
4
20
V
V
ns
ns
ns
see Fig.4
see Fig.4
see Fig.5
t
hHO
see Fig.5
4
ns
t
dLO
see Fig.5
20
ns
t
hLO
see Fig.5
4
ns
RED, HD and VD (C
L
= 15 pF; I
OL
= 2 mA; R
L
= 2 k
); timing referred to CLK32;
see Fig.4
V
OH
V
OL
t
d(o)
t
h(o)
SR
HIGH-level output voltage
LOW-level output voltage
output delay time
output hold time
slew rate
2.4
4
200
500
0.4
20
700
V
V
ns
ns
see Fig.4
see Fig.4
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ns
mV
ns
mV
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