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參數(shù)資料
| 型號(hào)： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
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1999 Aug 25
31
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
Colour correction
P
ROGRAMMING SELECTOR
,
ACTIVATION
Colour correction activation
Straight colour processing
Colour substitution enabled
Blue component programming
Red component correction colour writing disabled
Red component correction colour writing enabled
Green component programming
Red component correction colour writing disabled
Red component correction colour writing enabled
Red component programming
Red component correction colour writing disabled
Red component correction colour writing enabled
47
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
C
OLOUR INDEX FOR LOOK
-
UP TABLE WRITING
Colour component look-up table index
48
W
D7 to D0
C
OLOUR VALUE FOR LOOK
-
UP TABLE WRITING
Colour component substitution value
49
W
D7 to D0
Memory controller unit
G
ENERAL CONFIGURATION
External memory data bus width
32 bits (two 16-bit channels)
48 bits (three 16-bit channels)
64 bits (four 16-bit channels)
do not use
50
W
D3 and D2
D3 = 0 and D2 = 0
D3 = 0 and D2 = 1
D3 = 1 and D2 = 0
D3 = 1 and D2 = 1
A
CCESS BURST LENGTH
Number of bursts per read/write access to SDRAM
51
W
D3 to D0
SDRAM
BURST LENGTH
SDRAM burst length
SDRAM initialization code for burst length
52
W
D3 to D0
D6 to D4
SDRAM
TIMING PARAMETER
1;
SEE
T
ABLE
10
Active to read or write delay (t
RCD
) in clocks
CAS latency (CL) in clocks
53
W
D3 to D0
D6 to D4
SDRAM
TIMING PARAMETER
2;
SEE
T
ABLE
10
Precharge command period (t
RP
) in clocks
Active bank A to active band B command (t
RRD
) in clocks
54
W
D3 to D0
D7 to D4
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
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