參數(shù)資料
型號: SAA6713H
廠商: NXP Semiconductors N.V.
英文描述: XGA dual input flat panel controller
中文描述: 雙輸入的XGA液晶控制器
文件頁數(shù): 3/103頁
文件大?。?/td> 521K
代理商: SAA6713H
2004 Apr 05
3
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
1
FEATURES
Integrated triple Analog-to-Digital Converter (ADC) for
RGB analog sampling up to 110 MHz
Integrated PLL for dot clock recovery
Integrated single channel Digital Visual Interface
(DVI)
(1)
compliant digital serial interface up to 110 MHz
dot clock
Integrated composite sync slicer
High-bandwidth Digital Content Protection (HDCP)
(2)
Integrated sync-on-green separation
Support of Super Extended Graphics Adapter (SXGA)
input mode
Independent horizontal and vertical arbitrary ratio up
and downscaling
Video mode detection
Auto-adjustment support for sampling phase and
frequency, picture alignment and colour alignment
Advanced colour adjustment
Integrated On Screen Display (OSD) controller with
predefined and programmable font and bit-mapped
graphics, as well as a hardware overlay cursor
10-bit gamma correction
Support for 6-bit and 8-bit panels by temporal dithering
Freely programmable output timing supports displays of
virtually any manufacturer
Directly interfaces row and column drivers (TCON),
versatile timing generation
Programmable output pin ordering
Adjustable output pin ordering
High-speed I
2
C-bus interface up to 3.4 Mbits/s
Event driven interrupt generation for easy interfacing
with microcontroller software.
2
GENERAL DESCRIPTION
The SAA6713H is a dual input single-chip Thin Film
Transistor(TFT)displaycontroller ICwithanalogVGAand
digital DVI 1.0 standard input capabilities. Additionally, the
SAA6713H includes a wide range of functions for
processing and the measurement of incoming RGB data
according to the requirements of an XGA TFT display.
Covered functions are accurate measurements for the
horizontal and vertical input frequencies to determine the
incoming video mode and advanced auto-adjustment
features that provide all data for a fast and accurate
adjustment of frequency, phase and gain settings. Both
units are able to generate interrupts for easy interfacing
with a system microcontroller with separately maskable
interrupt conditions.
The input section handles incoming data up to SXGA
resolution that can be downscaled individually in width and
heighttofittotheconnectedpanelresolution.Independent
horizontal and vertical upscaling with enhanced
programmable filter possibilities provides the IC’s core
functionality of high-quality scaling. Picture quality is
further supported by an enhanced colour management
including a 10-bit gamma correction function. A
sophisticated dithering unit allows the use of low-end 6-bit
panels while keeping up the high quality image
impression.
An advanced OSD generator is integrated with a fixed
12
×
18 ROM font consisting of 179 ANSI characters,
77 Japanese characters, 48 multicolour icons and
48 single colour icons. In addition to these fixed size
characters another 112 different border characters can be
generated in any desired font size between 8
×
8 and
32
×
32pixels.Another38 specialcharactersareprovided
particularly for multicolour slider icons that can be
parametrized in size and style. For higher flexibility of the
OSD appearance a downloadable mixed multicolour or
single colour font with any programmable character size
between 8
×
8 to 32
×
32 pixels and up to four colours per
character can be used and displayed together with the
predefined ROM characters. A special bitmap organized
graphical OSD with up to 16 individual colours allows to
include graphic items like company logos, while a double
buffered OSD cursor gives the ability to use animated
pointers within an on screen menu. The panel timing
interface can not only drive today’s common timing
controller based panel interfaces, but it has also the
capability to directly drive the row and column drivers of a
panel itself. An adjustable output pin ordering guarantees
easy board layout with any type of panel connector.
(1) DVI specification published by Digital Display Working Group
(DDWG) promoters and may have related patents and/or
patent applications.
(2) HDCP is software designed by Intel/Silicon Image. All
trademark rights belong to the respective producers.
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