2004 Jun 29
5
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3
GENERAL DESCRIPTION
The SAA7108AE; SAA7109AE is a new multi-standard
video decoder and encoder chip, offering high quality
video input and TV output processing as required by
PC-99 specifications. It enables hardware manufacturers
to implement versatile video functions on a significantly
reduced printed-circuit board area at very competitive
costs.
Separate pins for supply voltages as well as for I
2
C-bus
control and boundary scan test have been provided for the
video encoder and decoder sections to ensure both
flexible handling and optimized noise behaviour.
The
video encoder
is used to encode PC graphics data at
maximum1280
×
1024resolution(optionally1920
×
1080
interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals.
A programmable scaler and anti-flicker filter (maximum
5 lines) ensures properly sized and flicker-free TV display
as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 1280
×
1024
resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this
port can provide Y, P
B
and P
R
signals for HDTV monitors.
The encoder section includes a sync/clock generator and
on-chip DACs.
All inputs intended to interface to the host graphics
controller are designed for low-voltage signals down to
1.1 V and up to 3.45 V.
The
video decoder
, a 9-bit video input processor, is a
combination of a 2-channel analog pre-processing circuit
including source selection, anti-aliasing filter and
Analog-to-Digital Converter (ADC), automatic clamp and
gain control, a Clock Generation Circuit (CGC), and a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
combination PAL N, NTSC M, NTSC-Japan, NTSC N,
NTSC 4.43 and SECAM).
The decoder includes a brightness, contrast and
saturation control circuit, a multi-standard VBI data slicer
and a 27 MHz VBI data bypass. The pure 3.3 V (5 V
compatible) CMOS circuit SAA7108AE; SAA7109AE,
consisting of an analog front-end and digital video
decoder, a digital video encoder and analog back-end, is a
highly integrated circuit especially designed for desktop
video applications.
The decoder is based on the principle of line-locked clock
decoding and is able to decode the colour of PAL, SECAM
and NTSC signals into ITU-R BT.601 compatible colour
component values.
The encoder can operate fully independently at its own
variable pixel clock, transporting graphics input data, and
at the line-locked, single crystal-stable video encoding
clock.
As an option, it is possible to slave the video PAL/NTSC
encodingtothevideodecoderclockwiththeencoderFIFO
acting as a buffer to decouple the line-locked decoder
clock from the crystal-stable encoder clock.
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ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7108AE
SAA7109AE
BGA156
plastic ball grid array package; 156 balls; body 15
×
15
×
1.15 mm
SOT472-1