- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄372113 > SAA7109A (NXP Semiconductors N.V.) HD-CODEC PDF資料下載
參數(shù)資料
| 型號(hào)： | SAA7109A |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | HD-CODEC |
| 中文描述： | 高清解碼器 |
| 文件頁(yè)數(shù)： | 57/197頁(yè) |
| 文件大小： | 983K |
| 代理商： | SAA7109A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)當(dāng)前第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)
2004 Jun 29
57
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
In VBI pass through operation the processing of prescaler
and vertical scaling has to be disabled, however the
horizontal fine scaling VPD can be activated. Upscaling
(oversampling, zooming), free of frequency folding, up to
factor 3.5 can be achieved, as required by some software
data slicing algorithms.
These raw samples are transported through the image
port as valid data and can be output as Y only format. The
lines are framed by SAV and EAV codes.
9.3.1
A
CQUISITION CONTROL AND TASK HANDLING
(
SUBADDRESSES
80H, 90H, 91H, 94H
TO
9FH
AND
C4H
TO
CFH)
The acquisition control receives horizontal and vertical
synchronization signals from the decoder section or from
the X port. The acquisition window is generated via pixel
and line counters at the appropriate places in the data
path. Only qualified pixels and lines (lines with qualified
pixel) are counted from the X port.
The acquisition window parameters are as follows:
Signal source selection: input video stream and formats
from the decoder, or from the X port (programming bits
SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0])
Remark
: The input of raw VBI data from the internal
decoder should be controlled via the decoder output
formatter and the LCR registers (see Section 9.2)
Vertical offset: defined in lines of the video source,
parameter YO[11:0] 99H[3:0] 98H[7:0]
Vertical length: defined in lines of the video source,
parameter YS[11:0] 9BH[3:0] 9AH[7:0]
Vertical length: defined in number of target lines, as a
result of vertical scaling, parameter YD[11:0] 9FH[3:0]
9EH[7:0]
Horizontal offset: defined in number of pixels of the
video source, parameter XO[11:0] 95H[3:0] 94H[7:0]
Horizontal length: defined in number of pixels of the
video source, parameter XS[11:0] 97H[3:0] 96H[7:0]
Horizontal destination size: defined in target pixels after
fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0].
The source start offset XO(11:0) and YO(11:0) opens the
acquisition window, and the target size (XD11 to XD0,
YD11 to YD0) closes the window, however the window is
cut vertically if there are less output lines than required.
The trigger events for the pixel and line counts are the
horizontal and vertical reference edges as defined in
subaddress 92H.
The task handling is controlled by subaddress 90H;
see Section 9.3.1.2.
9.3.1.1
Input field processing
The trigger event for the field sequence detection from
external signals (X port) are defined in subaddress 92H.
The state of the scalers horizontal reference signal at the
time of the vertical reference edge is taken from the X port
asfieldsequenceidentifier(FID).Forexample,ifthefalling
edge of the XRV input signal is the reference and the state
of XRH input is logic 0 at that time, the detected field ID is
logic 0.
The bits XFDV[92H[7]] and XFDH[92H[6]] define the
detection event and state of the flag from the X port. For
the default setting of XFDV and XFDH at ‘00’ is taken from
the state of the horizontal input at the falling edge of the
vertical input.
The scaler gets corresponding field ID information directly
from the SAA7108AE; SAA7109AE decoder path.
The FID flag is used to determine whether the first or
second field of a frame is going to be processed within the
scaler, and it is also used as trigger conditions for the task
handling (see bits STRC[1:0] 90H[1:0]).
According to ITU 656, FID at logic 0 means first field of a
frame. To ease the application, the polarities of the
detection results on the X port signals and the internal
decoder ID can be changed via XFDH.
As the V sync from the decoder path has a half line timing
(due to the interlaced video signal), but the scaler
processing only recognises full lines, during 1st fields from
the decoder the line count of the scaler can possibly shift
by one line, compared to the 2nd field. This can be
compensated for by switching the vertical trigger event, as
defined by XDV0, to the opposite V sync edge or by using
the vertical scalers phase offsets. The vertical timing of the
decoder can be seen in Figs 30 and 31.
As the horizontal and vertical reference events inside the
ITU 656 data stream (from X port) and the real-time
reference signals from the decoder path are processed
differently, the trigger events for the input acquisition also
have to be programmed differently.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109AE | HD-CODEC |
| SAA7110A | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111A | Enhanced Video Input Processor EVIP |
| SAA7111AH | Enhanced Video Input Processor EVIP |
| SAA7111AHZ | GT 13C 13#16 SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE/V1,518 | 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109AE/V1,557 | 功能描述:視頻 IC HD- VIDEO CODEC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109AE/V1/G | 功能描述:視頻 IC PC CODEC (W/OUT MICROVISION) RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109AE/V1/G,518 | 功能描述:視頻 IC SAA7109AE/LBGA156/REEL13DP//V1 RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。