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參數(shù)資料
| 型號(hào)： | SAA7134HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | PCI audio and video broadcast decoder |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 233K |
| 代理商： | SAA7134HL |
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SAA7134HL_4
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 31 March 2006
20 of 51
Philips Semiconductors
SAA7134HL
PCI audio and video broadcast decoder
6.4.3
DMA and configurable FIFO
The SAA7134HL supports seven DMA channels to master-write captured active video,
audio, raw VBI and DTV/DVB Transport Streams (TS) into the PCI memory. Each DMA
channel contains inherently the definition of two buffers, e.g. for odd and even fields in
case of interlaced video, or two alternating buffers to capture continuous audio stream.
The DMA channels share in time and space one common FIFO pool of 256 Dwords
(1024 bytes) total. It is freely configurable how much FIFO capacity can be associated
with which DMA channel. Furthermore, a preferred minimum burst length can be
programmed, i.e. the amount of data to be collected before the request for the PCI-bus is
issued. This means that latency behavior per DMA channel can be tailored and optimized
for a given application.
In the event that a FIFO of a certain channel overflows due to latency conflict on the bus,
graceful overflow recovery is applied. The amount of data that gets lost because it could
not be transmitted, is monitored (counted) and the PCI-bus address pointer is
incremented accordingly. Thus new data will be written to the correct memory place, after
the latency conflict is resolved.
6.4.4
Virtual and physical addressing
Most operating systems allocate memory to requesting applications for DMA as
continuous ranges in virtual address space. The data flow over the PCI-bus points to
physical addresses, usually not continuous and split in pages of 4 kB (Intel architecture,
most UNIX systems, Power PC).
The association between the virtual (logic) address space and the fragmented physical
address space is defined in page tables (system files); see
Figure 8
.
The SAA7134HL incorporates hardware support (MMU) to translate virtual to physical
addresses on the fly, by investigating the related page table information. This hardware
support reduces the demand for real-time software interaction and interrupt requests, and
therefore saves system resources.
Table 13:
Power state
D0
Power management table
Description
Normal operation: all functions accessible and programmable. The default setting
after reset and before driver interaction (D0 un-initialized) switches most of the
circuitry of the SAA7134HL into the Power-down mode, effectively such as
D3-hot.
First step of reduced power consumption: no functional operation. Program
registers are not accessible, but content is maintained. Most of the circuitry of the
SAA7134HL is disabled with exception of the crystal and real-time clock
oscillators, so that a quick recovery from D1 to D0 is possible.
Second step of reduced power consumption: no functional operation. Program
registers are not accessible, but content is maintained. All functional circuitry of
the SAA7134HL is disabled, including the crystal and clock oscillators.
Lowest power consumption: no functional operation. The content of the
programming registers gets lost and is set to default values when returning to D0.
D1
D2
D3-hot
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7134HL/V1,518 | 功能描述:視頻 IC PCI 9-BIT VID/STEREO RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7134HL/V1,557 | 功能描述:視頻 IC PCI 9-BIT VID/STEREO RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7134HLBE | 功能描述:視頻 IC PCI 9-BIT VID/STEREO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7134HLBE-T | 功能描述:視頻 IC PCI 9-BIT VID/STEREO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7135 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip, analog TV video/stereo DECODER |
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