參數(shù)資料
型號(hào): SAA7134HL
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: PCI audio and video broadcast decoder
文件頁(yè)數(shù): 41/51頁(yè)
文件大?。?/td> 233K
代理商: SAA7134HL
SAA7134HL_4
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 31 March 2006
41 of 51
Philips Semiconductors
SAA7134HL
PCI audio and video broadcast decoder
The full-scale level for analog audio signals V
FS
= 0.8 V (RMS). The nominal level at the digital crossbar switch is defined at
15 dB (FS).
Nominal audio input levels: external, mono, V
i
= 280 mV (RMS);
9 dB (FS).
[12] The analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) are supported by two input levels: 1 V (RMS) and 2 V (RMS),
selectable independently per stereo input pair, LEFT1, RIGHT1 and LEFT2, RIGHT2.
[13] V
DDA
= 3.3 V; settings in accordance with B/G standard; FM deviation is
±
50 kHz; f
mod
= 1 kHz; FM sound parameters in accordance
with system A2; NICAM in accordance with EBU specification; 1 k
measurement source resistance for AF inputs;
V
i(SIF)
= 300 mV (p-p); programming registers AGCOFF = 0 and AGCSLOW = 1; level and gain settings according to
Table note 11
; for
external components see the application diagram in SAA7130HL and SAA7134HL application notes; unless otherwise specified.
[14] The NICAM values are in accordance with the EBU specification. Audio performance is limited by the dynamic range of the NICAM 728
system. Due to companding, the quantization noise is never lower than
62 dB with respect to the input level.
[15] FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output; V
o
= 0.8 V (RMS) of
modulated channel.
[16] FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output; V
o
= 0.8 V (RMS)
of modulated channel.
[17] The definition of the duty factor:
[18] The output timing must be measured with the load of a 30 pF capacitor to ground and a 500
resistor to 1.4 V.
[19] Signal V_CLK inverted; not delayed (default setup).
[20] t
PD
= 6 ns + 0.6
×
T
ADC_CLK
in ns (T
ADC_CLK
= 28 ns).
δ
t
H
T
cy
-------
=
Fig 14. PCI I/O timing
mgg280
t
val
t
on
t
su
t
h
t
off
1.5 V
1.5 V
1.5 V
1.5 V
2.4 V
0.4 V
0.4 V
2.4 V
CLK
OUTPUT
DELAY
3-STATE
OUTPUT
INPUT
input valid
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