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SAA7134HL_4
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 31 March 2006
40 of 51
Philips Semiconductors
SAA7134HL
PCI audio and video broadcast decoder
[1]
Input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs.
[2]
Pins without pull-up resistors must have a 3 mA output current. Pins requiring pull-up resistors must have 6 mA; these are
pins FRAME#, TRDY#, IRDY#, DEVSEL#, SERR#, PERR#, INT_A and STOP#.
[3]
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range.
[4]
REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than bused signals. GNT# has a
setup time of 10 ns. REQ# has a setup time of 12 ns.
[5]
For purposes of active or float timing measurements, the high-impedance or ‘off’ state is defined to be when the total current delivered
through the device is less than or equal to the leakage current specification.
[6]
RST_N is asserted and de-asserted asynchronously with respect to CLK.
[7]
All output drivers floated asynchronously when RST_N is active.
[8]
V
DD(I2C)
is the extended pull-up voltage of the I
2
C-bus (3.3 Vor 5 V bus).
Nominal analog video input signal is to be terminated by 75
that results in 1 V (p-p) amplitude. This termination resistor should be split
into 18
and 56
, and the dividing tap should feed the video input pin, via a coupling capacitor of 47 nF, to achieve a control range
from
3 dB (attenuation) to +6 dB (amplification) for the internal automatic gain control. See also Application note SAA7130HL/34HL
[9]
[10] See User manual SAA7130HL/34HLfor Anti-Alias Filter (AAF).
[11] Definition of levels and level setting:
VSB data output signals with respect to signal ADC_CLK
C
L
load capacitance
t
h
data hold time
t
PD
propagation delay from
positive edge of
signal ADC_CLK
TS capture inputs with parallel transport streaming (TS-P); e.g. DVB applications
Clock input signal TS_CLK on pin GPIO20; see
Figure 16
T
cy
cycle time
δ
duty factor
t
r
rise time
0.8 V to 2.0 V
t
f
fall time
2.0 V to 0.8 V
Data and control input signals on TS-P port (with respect to signal TS_CLK) on pins GPIO0 to GPIO7, GPIO16, GPIO19
and GPIO22; see
Figure 16
t
su(D)
input data setup time
t
h(D)
input data hold time
TS capture inputs with serial transport streaming (TS-S); e.g. DVB applications
Clock input signal TS_CLK on pin GPIO20; see
Figure 16
T
cy
cycle time
δ
duty factor
t
r
rise time
0.8 V to 2.0 V
t
f
fall time
2.0 V to 0.8 V
Data and control input signals on TS-S port (with respect to signal TS_CLK) on pins GPIO16, GPIO19, GPIO21 and
GPIO22; see
Figure 16
t
su(D)
input data setup time
t
h(D)
input data hold time
25
-
-
-
50
-
23
pF
ns
ns
inverted and not delayed
inverted and not delayed
[18]
5
[18] [20]
-
-
333
-
-
-
-
60
5
5
ns
%
ns
ns
[17]
40
-
-
2
5
-
-
-
-
ns
ns
37
-
-
-
-
-
60
5
5
ns
%
ns
ns
[17]
40
-
-
2
5
-
-
-
-
ns
ns
Table 19:
V
DDD
= 3.0 V to 3.6 V; V
DDA
= 3.0 V to 3.6 V; T
amb
= 25
°
C; unless otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit