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參數資料
| 型號： | SAA7706H/N210S,518 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 18/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CAR RADIO 80QFP |
| 標準包裝： | 500 |
| 類型： | 汽車信號處理器 |
| 接口： | I²C，I²:S，LSB，SPDIF |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-BQFP |
| 供應商設備封裝： | 80-QFP（14x20） |
| 包裝： | 帶卷 (TR) |
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2001 Mar 05
25
Philips Semiconductors
Product specication
Car radio Digital Signal Processor (DSP)
SAA7706H
8.14
Digital serial inputs/outputs and SPDIF inputs
8.14.1
GENERAL DESCRIPTION DIGITAL SERIAL AUDIO
INPUTS
/OUTPUTS
For communication with external digital sources a digital
serial bus is implemented. It is a serial 3-line bus, having
one line for data, one line for clock and one line for the
word select. For external digital sources the SAA7706H
acts as a slave, so the external source is master and
supplies the clock.
The digital serial input is capable of handling multiple input
formats. The input is capable of handling Philips I2S-bus
and LSB-justified formats of 16, 18, 20 and 24 bits word
sizes. The sampling frequency can be either
44.1 or 48 kHz. See Fig.15 for the general waveform
formats of all possible formats.
The number of bit clock (BCK) pulses may vary in the
application. When the applied word length is smaller than
24 bits (internal resolution of DSP2), the LSB bits will get
internally a zero value; when the applied word length
exceeds 24 bits then the LSBs are skipped.
It should be noted that:
Two digital sources can not be used at the same time
Maximum number of bit clocks per word select (WS) is
limited to 64
The word select (WS) must have a duty cycle of 50%.
8.14.2
GENERAL DESCRIPTION SPDIF INPUTS (SPDIF1
AND
SPDIF2)
For communication with external digital sources also an
SPDIF input can be used. The two SPDIF input pins can
be connected via an analog multiplexer to the SPDIF
receiver. It is a receiver without an analog PLL that
samples the incoming SPDIF with a high frequency. In this
way the data is recovered synchronously on the applied
system clock.
From the SPDIF signal a three wire serial bus
(e.g. I2S-bus) is made, consisting of a word select, data
and bit clock line. The sample frequency fs depends solely
on the SPDIF signal input accuracy and both 44.1 and
48 kHz are supported.
This chip does not handle the user data bits, channel
status bits and validity bits of the SPDIF stream, but only
the audio is given at its outputs. Some rom_codes do take
care of the pre-emphasis bit of the SPDIF stream.
The bits in the audio space are always decoded regardless
of any status bits e.g. ‘copy protected’, ‘professional mode’
or ‘data mode’. The DAC is not muted in the event of a
non-linear PCM audio, however the bit is observable via
the I2C-bus. A few other channel status bits are available.
There are 5 control signals available from the SPDIF input
stage. These are connected to flags of DSP2. For more
details see separate manual.
These 5 control signals are:
Signals to indicate the sample frequency of the SPDIF
signal: 44.1 and 48 kHz (32 kHz is not supported)
A lock signal indicating if the SPDIF input is in lock
The pre-emphasis bit of the SPDIF audio stream
The pcm_audio/non-pcm_audio bit indicating if an audio
or data stream is detected. The FSDAC output will not
be muted in the event of a non-audio PCM stream. This
status bit can be read via the I2C-bus, the
microcontroller can decide to mute the DAC (via
pin POM).
The design fulfils the digital audio interface specification
“IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2,
part 3, consumer applications”.
It should be noted that:
The SPDIF input may only be used in the ‘consumer
mode’ specified in the digital audio interface
specification
Only one of the two SPDIF sources can be used
(selected) at the same time
The FSDAC will not (automatically) be muted in the
event of a non-audio stream
Two digital sources can not be used at the same time
Supported sample frequencies are 44.1 and 48 kHz.
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