參數(shù)資料
型號(hào): SAA7706H/N210S,518
廠商: NXP Semiconductors
文件頁數(shù): 21/52頁
文件大小: 0K
描述: IC DSP CAR RADIO 80QFP
標(biāo)準(zhǔn)包裝: 500
類型: 汽車信號(hào)處理器
接口: I²C,I²:S,LSB,SPDIF
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-BQFP
供應(yīng)商設(shè)備封裝: 80-QFP(14x20)
包裝: 帶卷 (TR)
2001 Mar 05
28
Philips Semiconductors
Product specication
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
10
70
50
54
62
MGT472
58
64
52
60
56
30
20
10
60
50
40
0
f (kHz)
α
(dB)
Fig.17 Detailed frequency response curve RDS channel.
The quadrature mixer converts the RDS band to the
frequency spectrum around 0 Hz and contains the
appropriate Q/I signal filters. The final decoder with
CORDIC recovers the clock and data signals. These
signals are output on pins RDS_CLOCK and RDS_DATA.
In the event of FM-stereo reception the clock of the total
chip is locked to the stereo pilot (19 kHz multiple). In the
event of FM-mono the DCS loop keeps the DCS clock
around the same 19 kHz multiple. In all other cases like
AM reception or tape, the DCS circuit has to be set in a
preset position by means of an I2C-bus bit. Under these
conditions the RDS system is always clocked by the DCS
clock in a 38 kHz (4
× 9.5 kHz) based sequence.
8.15.2
TIMING OF CLOCK AND DATA SIGNALS
The timing of the clock and data output is derived from the
incoming data signal. Under stable conditions the data will
remain valid for 400
s after the clock transition. The
timing of the data change is 100
s before a positive clock
change. This timing is suited for positive as well as
negative triggered interrupts on a microcontroller. The
RDS timing is shown in Fig.18. During poor reception it is
possible that faults in phase occur, then the duty cycle of
the clock and data signals will vary from minimum
0.5 times to a maximum of 1.5 times the standard clock
periods. Normally, faults in phase do not occur on a cyclic
basis.
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