參數(shù)資料
型號: SAA8115HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Digital Camera USB Interface(數(shù)字照相USB接口)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁數(shù): 6/56頁
文件大小: 177K
代理商: SAA8115HL
2000 Jan 27
6
Philips Semiconductors
Preliminary specification
Digital camera USB interface
SAA8115HL
7
PINNING
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
C3
C2
C1
C4
SHUTTER
GND1
V
DD1
RG
FS
FCDS
CLK1
DCP
BCP
VD
HD
V
DD2
CLK2
GND2
YUV0
YUV1
YUV2
YUV3
DGND1
V
DDD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
O
O
O
O
O
P
P
O
O
O
O
O
O
O
O
P
O
P
I
I
I
I
P
P
horizontal CCD transfer pulse output
horizontal CCD transfer pulse output (FH1)
horizontal CCD transfer pulse output (FH2)
horizontal CCD transfer pulse output
shutter control output for CCD charge reset
ground 1 for output buffers
supply voltage 1 for output buffers
reset output for CCD output amplifier gate
data sample-and-hold pulse output to TDA8784/87 (SHD)
preset sample-and-hold pulse output to TDA8784/87 (SHP)
pixel clock to TDA8784/87 and SAA8112HL
dummy clamp pulse output to TDA8784/87
optical black clamp pulse output to TDA8784/87
vertical definition pulse to SAA8112HL
horizontal definition pulse to SAA8112HL
supply voltage 2 for output buffers
double pixel clock to SAA8112HL
ground 2 for output buffers
multiplexed YUV bit 0
multiplexed YUV bit 1
multiplexed YUV bit 2
multiplexed YUV bit 3
digital ground 1 for input buffers, predrivers and for the digital core
digital supply voltage 1 for input buffers, predrivers and one part of the digital
core
multiplexed YUV bit 4
multiplexed YUV bit 5
multiplexed YUV bit 6
multiplexed YUV bit 7
digital ground 2 for input buffers, predrivers and for the digital core
line-locked clock input (delayed CLK2) for YUV-port from SAA8112HL
horizontal reference input for YUV-port from SAA8112HL
vertical synchronization input for YUV-port from SAA8112HL
Power-on reset input (for video processing and PPG)
data input/output for SNERT-interface (communication between SAA8115HL
and SAA8112HL)
clock input for SNERT-interface (communication between SAA8115HL and
SAA8112HL)
reset input for SNERT-interface (communication between SAA8115HL and
SAA8112HL)
YUV4
YUV5
YUV6
YUV7
DGND2
LLC
HREF
VS
RESET
SNDA
25
26
27
28
29
30
31
32
33
34
I
I
I
I
P
I
I
I
I
I/O
SNCL
35
I
SNRES
36
I
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