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| 型號： | SAB-XC164SM-8F40F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 18/66頁 |
| 文件大?。?/td> | 613K |
| 代理商： | SAB-XC164SM-8F40F |
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XC164SM
Derivatives
Functional Description
Data Sheet
23
V1.0, 2005-11
The XC164SM also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 3-3 shows all of the possible exceptions or error conditions that can arise during
run-time:
Table 3-3
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Location
1)
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
W-dog Timer Overflow
–
RESET
xx’0000
H
xx’0000
H
xx’0000
H
00
H
00
H
00
H
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Software Break
NMI
STKOF
STKUF
SOFTBRK
NMITRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008
H
xx’0010
H
xx’0018
H
xx’0020
H
02
H
04
H
06
H
08
H
II
Class B Hardware Traps:
Undefined Opcode
PMI Access Error
Protected Instruction
Fault
Illegal Word Operand
Access
UNDOPC
PACER
PRTFLT
ILLOPA
BTRAP
xx’0028
H
xx’0028
H
xx’0028
H
xx’0028
H
0A
H
0A
H
0A
H
0A
H
I
Reserved
–
[2C
H - 3CH][0BH -
0F
H]
–
Software Traps
TRAP Instruction
––
Any
[xx’0000
H -
xx’01FC
H]
in steps of
4
H
Any
[00
H -
7F
H]
Current
CPU
Priority
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