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參數資料
| 型號： | SAB-XC164SM-8F40F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數： | 36/66頁 |
| 文件大?。?/td> | 613K |
| 代理商： | SAB-XC164SM-8F40F |
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XC164SM
Derivatives
Functional Description
Data Sheet
39
V1.0, 2005-11
3.13
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC164SM with high flexibility. The master clock
f
MC
is the reference clock signal and is output to the external system. The CPU clock
f
CPU
and the system clock
f
SYS are derived from the master clock either directly (1:1) or via a
2:1 prescaler (
f
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
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