參數(shù)資料
型號： SAH-XC2712X-8F66R
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38
文件頁數(shù)： 81/103頁
文件大?。?/td> 2957K
代理商： SAH-XC2712X-8F66R
XC2712X
XC2000 Family / Compact Line
Electrical Parameters
PRELIMINARY
Data Sheet
75
V1.0, 2010-12
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
f
SYS = fIN.
The frequency of
f
SYS is the same as the frequency of fIN. In this case the high and low
times of
f
SYS are determined by the duty cycle of the input clock fIN.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived from the internal clock source through the output
prescaler K1 (= K1DIV+1):
f
SYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of
f
SYS equals the frequency of fOSC. In
this case the high and low times of
f
SYS are determined by the duty cycle of the input
clock
f
OSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f
SYS = fOSC / 1024.
4.6.2.1
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (
f
SYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P
× K2)).
The input clock can be derived from the on-chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of
f
SYS so that it is
locked to
f
IN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the given circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 16).
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