參數(shù)資料
型號: SAK-TC1782-320F180HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 180 MHz, RISC MICROCONTROLLER, PQFP176
封裝: GREEN, PLASTIC, LQFP-176
文件頁數(shù): 106/113頁
文件大小: 3371K
代理商: SAK-TC1782-320F180HL
TC1782
Electrical ParametersAC Parameters
Target Data Sheet/ACDC Target Specification 51
V 0.7 Preliminary, 2010-03
1.3.8.2
Micro Second Channel (MSC) Interface Timing
TCLK fall time
t
14 CC
16
3)
ns
TDATA/TVALID output
delay time
t
15 CC
-3
4.4
ns
TREADY setup time
before TCLK rising edge
t
16 SR
18
ns
TREADY hold time after
TCLK rising edge
t
17 SR
-4
ns
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
Table 25
MSC Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
FCLP clock period
1)2)
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1
ξφ
TMSC
t
40 CC
2 x
T
MSC
3)
3) TMSC = TSYS = 1 / fSYS.
ns
SOP/ENx outputs delay
from FCLP rising edge
t
45 CC
-10
10
ns
SDI bit time
t
46 CC
8 x
T
MSC
ns
SDI rise time
t
48 SR
100
ns
SDI fall time
t
49 SR
100
ns
Table 24
MLI Transmitter (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
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