參數(shù)資料
型號： SAK-TC1782-320F180HL
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 180 MHz, RISC MICROCONTROLLER, PQFP176
封裝： GREEN, PLASTIC, LQFP-176
文件頁數(shù)： 110/113頁
文件大小： 3371K
代理商： SAK-TC1782-320F180HL
TC1782
Electrical ParametersAC Parameters
Target Data Sheet/ACDC Target Specification 55
V 0.7 Preliminary, 2010-03
1.3.8.4
ERAY Interface Timing
C
L = 25 pF
The ERAY interface is only available for the SAK-TC1782-320F180HL.
Table 27
ERAY Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
Time span from last BSS
to FES without the
influence of quartz
tolerancies (d10Bit_TX)
1)
1) This includes the PLL_ERAY accumulated jitter.
t
60 CC
997.25
1002.2
5
ns
TxD data valid from
fsample flip flop txd_reg
TxDA, TxDB
(dTxAsym)
2)3)
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |
t
FA2 - tRA2| 1 ns.
t
61-t62
CC
1.5
ns
Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
Time span between last
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)
4) The Min limit correspond to 30% *
V
DDP FlexRay standard input thresholds. The Max limit correspond to 70%
*
V
DDP FlexRay standard input thresholds. Due to different input thresholds for this product, a correction of -
0.5 ns and +0.1 ns has been applied.
5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% *
V
DDP to 80% * VDDP, according to the FlexRay
Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have
to satisfy the following inequality: -1.6ns
t
FA2 - tRA2 1.3ns.
t
63 SR
967
1046.1 ns
RxD capture by fsample
(RxDA/RxDB sampling
flip-flop) (dRxAsym)
6)
6) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% *
V
DDP to 80% * VDDP, according to the FlexRay
Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have
to satisfy the following inequality: -1.6ns
t
FA2 - tRA2 1.3ns.
t
64-t65
CC
3.0
ns
Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
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