參數(shù)資料
型號(hào)： SAK-XC164CS-32F20F
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TQFP-100
文件頁數(shù)： 63/81頁
文件大?。?/td> 1106K
代理商： SAK-XC164CS-32F20F
XC164-32
Derivatives
Electrical Parameters
Data Sheet
64
V1.1, 2006-08
CPU and EBC are clocked with the CPU clock signal
f
CPU. The CPU clock can have the
same frequency as the master clock (
f
CPU = fMC) or can be the master clock divided by
two:
f
CPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
f
SYS which has the same
frequency as the CPU clock signal
f
CPU.
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
MC = fOSC / ((PLLIDIV+1) × (PLLODIV+1)).
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of
f
MC
directly follows the frequency of
f
OSC so the high and low time of fMC is defined by the duty
cycle of the input clock
f
OSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
MC = fOSC / ((3 + 1) × (14 + 1)) = fOSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (
f
MC = fOSC × F) which results from the input divider, the multiplication factor, and
the output divider (F = PLLMUL+1 / (PLLIDIV+1
× PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
f
MC is constantly adjusted so it
is locked to
f
OSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
f
CPU is derived from
f
MC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 16).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAK-XC164CS-32F20F BB-A 功能描述:16位微控制器 - MCU 16BIT SNGL CHIP 5V 20MHz Flash RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
SAK-XC164CS-32F20F BB-A TR 制造商:Infineon Technologies AG 功能描述:
SAKXC164CS32F20FBB-A 制造商:Infineon Technologies AG 功能描述:
SAK-XC164CS-32F40F 制造商:Rochester Electronics LLC 功能描述:- Bulk
SAK-XC164CS-32F40F BB 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit XC166 CISC/DSP/RISC 256KB Flash 2.5V/5V 100-Pin TQFP
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