參數(shù)資料
型號: SAK-XC2237M-104F40L
廠商: Infineon Technologies
文件頁數(shù): 29/107頁
文件大小: 0K
描述: IC MCU 16BIT 320KB FLASH 64LQFP
標準包裝: 1,900
系列: XC22xxM
核心處理器: C166SV2
芯體尺寸: 16/32-位
速度: 40MHz
連通性: CAN,EBI/EMI,I²C,LIN,SPI,SSC,UART/USART,USI
外圍設備: I²S,POR,PWM,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 832KB(832K x 8)
程序存儲器類型: 閃存
RAM 容量: 50K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 帶卷 (TR)
其它名稱: SP000720382
XC2238M, XC2237M
XC2000 Family / Base Line
Functional Description
Data Sheet
28
V2.1, 2011-07
3
Functional Description
The architecture of the XC223xM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 4). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC223xM.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC223xM.
Figure 4
Block Diagram
DPRAM
CPU
PM
U
DM
U
ADC0
Module
10 -Bit
8-Bit
RTC
MCHK
Interrupt & PEC
EBC
LXBus Control
External Bus
Control
DSRAM
System Functions
Clock, Reset, Power
Control, StandBy RAM
OCDS
Debug Support
Interrupt Bus
Periph
eral
D
a
ta
Bu
s
Analog and Digital General Purpose IO (GPIO) Ports
MC_BL_BLOCKDIAGRAM
GPT
5
Timers
CC2
Modules
16
Chan.
LXB
u
s
WDT
Multi
CAN
Shared
MOs
for
Nodes
CCU6 x
Modules
3+1
Chan.
each
USICx
Modules
2
Chan.
each
PSRAM
Flash
Memory
IM
B
MAC Unit
MPU
ADC1
Module
10 -Bit
8-Bit
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