參數(shù)資料
型號: SAK-XC2237M-104F40L
廠商: Infineon Technologies
文件頁數(shù): 52/107頁
文件大?。?/td> 0K
描述: IC MCU 16BIT 320KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝: 1,900
系列: XC22xxM
核心處理器: C166SV2
芯體尺寸: 16/32-位
速度: 40MHz
連通性: CAN,EBI/EMI,I²C,LIN,SPI,SSC,UART/USART,USI
外圍設(shè)備: I²S,POR,PWM,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 832KB(832K x 8)
程序存儲器類型: 閃存
RAM 容量: 50K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 帶卷 (TR)
其它名稱: SP000720382
XC2238M, XC2237M
XC2000 Family / Base Line
Functional Description
Data Sheet
49
V2.1, 2011-07
3.12
Universal Serial Interface Channel Modules (USIC)
The XC223xM features the USIC modules USIC0, USIC1, USIC2. Each module
provides two serial communication channels.
The Universal Serial Interface Channel (USIC) module is based on a generic data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during runtime.
Figure 11
General Structure of a USIC Module
The regular structure of the USIC module brings the following advantages:
Higher flexibility through configuration with same look-and-feel for data management
Reduced complexity for low-level drivers serving different protocols
Wide range of protocols with improved performances (baud rate, buffer handling)
USIC_basic.vsd
Bu
s
I
n
te
rf
a
c
e
DBU
0
DBU
1
Control 0
Control 1
DSU
0
DSU
1
PPP_A
PPP_B
PPP_C
PPP_D
PPP_A
PPP_B
PPP_C
PPP_D
P
in
R
o
u
ti
n
g
S
h
el
l
Buffer & Shift Structure
Protocol Preprocessors
Pins
Bus
fsys
Fractional
Dividers
Baud rate
Generators
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