參數(shù)資料
型號: SAK-XC2285M-56F80LAA
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP144
封裝: 0.50 mm pitch, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 27/142頁
文件大?。?/td> 1112K
代理商: SAK-XC2285M-56F80LAA
XC2287M, XC2286M, XC2285M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Data Sheet
122
V2.0, 2009-03
Table 32
External Bus Cycle Timing for Lower Voltage Range
Parameter
Symbol
Limits
Unit Note
Min.
Typ.
Max.
Output valid delay for:
RD, WR(L/H)
t
10 CC
20
ns
Output valid delay for:
BHE, ALE
t
11 CC
21
ns
Address output valid delay for:
A23 … A16, A15 … A0
t
12 CC
22
ns
Address output valid delay for:
AD15 … AD0
t
13 CC
22
ns
Output valid delay for:
CS
t
14 CC
13
ns
Data output valid delay for:
AD15 … AD0 (write data, MUX)
t
15 CC
22
ns
Data output valid delay for:
D15 … D0 (write data, DEMUX)
t
16 CC
22
ns
Output hold time for:
RD, WR(L/H)
t
20 CC
-2
10
ns
Output hold time for:
BHE, ALE
t
21 CC
-2
10
ns
Address output hold time for:
AD15 … AD0
t
23 CC
-3
10
ns
Output hold time for:
CS
t
24 CC
-3
11
ns
Data output hold time for:
D15 … D0, AD15 … AD0
t
25 CC
-3
10
ns
Input setup time for:
READY, D15 … D0, AD15 … AD0
(read data)
t
30 SR
29
ns
Input hold time for:
READY, D15 … D0, AD15 … AD0
(read data)1)
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
t
31 SR
0
ns
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