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參數(shù)資料
| 型號： | SC-KIT-TBX |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/30頁 |
| 文件大小： | 0K |
| 描述： | TIMERBLOX SAMPLE KIT |
| 設(shè)計資源： | TimerBlox Designer |
| 特色產(chǎn)品： | TimerBlox? |
| 標準包裝： | 1 |
| 系列： | TimerBlox® |
| 主要目的： | 計時，時鐘振蕩器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC6990，LTC6991，LTC6992-1，LTC6993-2，LTC6994-1 |
| 已供物品： | 裸板，樣品 IC |
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LTC6990
18
6990fc
For more information www.linear.com/LTC6990
APPLICATIONS INFORMATION
Step 2: Calculate KVCO and f(0V)
Next,calculatetheintermediatevaluesKVCOandf(0V)using
Equations (3b) and (3c).
KVCO =
100kHz
10kHz
4V
1V
= 30kHz/V
f(0V) =100kHz + 30kHz/V 1V =130kHz
Step 3: Calculate and Select RVCO
The next step is to use Equation (3d) to calculate the cor-
rect value for RVCO.
RVCO =
1MHz 50k
8 1V 30kHz/V
= 208.333k
Select RVCO = 210k.
Step 4: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using Equation (3e).
RSET =
1MHz 50k
8 130kHz
1V 30kHz/V
(
)
= 62.5k
Select RSET = 61.9k
In this design example, with its wide 10:1 frequency
range, the potential output frequency error due to VSET
error alone ranges from less than ±1% when VCTRL is at
its minimum up to ±36% when VCTRL is at its maximum.
This error must be accounted for in the system design.
Depending on the application’s requirements, the non-
inverting VCO circuit in Figure 13 may be preferred for
this wide of a frequency variation as its maximum inac-
curacy due to VSET error is only ±9% and can be reduced
to only ±3% with a small change to the voltage tuning
range specification.
Reducing VSET Error Effects in VCO Applications
Figure 13 shows a VCO that reduces the effect of VSET
by adding an op-amp to make VCTRL dependent on VSET.
This circuit also has a positive transfer function (the out-
put frequency increases as VIN increases). Furthermore,
for positive VIN voltages, this circuit places the greatest
absolute frequency error at the highest output frequency.
Compared to the simple VCO circuit of Figure 11, the
absolute frequency error is unchanged. However, with
the maximum absolute frequency error (in Hertz) now
occurring at the highest output frequency, the relative
frequency error (in percent) is greatly improved.
Figure 13. VCO with Reduced VSET Sensitivity
6990 F13
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1F
R1
1M
R2
280k
DIVCODE = 3
(NDIV = 8, Hi-Z = 0)
RSET
249k
3V
RVCO
75k
–
+
3V
10kHz TO 100kHz
fOUT
VCTRL
VSET
1/2
LTC6078
R4
30.1k
C4
33pF
R3
100k
0.4V TO 4V
VIN
fOUT =
1MHz 50k
NDIV RVCO
RVCO
RSET
+
VIN
VSET
1
R4
R3
IF
R4
R3
=
RVCO
RSET
, THE EQUATION REDUCES TO:
fOUT =
1MHz 50k
NDIV RSET
VIN
VSET
= VIN 25kHz/V
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