For more information www.linear.com/LTC6990 6990 F17 LTC6990 OE GND SET OUT
參數(shù)資料
型號(hào)： SC-KIT-TBX
廠商： Linear Technology
文件頁(yè)數(shù)： 14/30頁(yè)
文件大?。?/td> 0K
描述： TIMERBLOX SAMPLE KIT
設(shè)計(jì)資源： TimerBlox Designer
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 1
系列： TimerBlox®
主要目的： 計(jì)時(shí)，時(shí)鐘振蕩器
嵌入式： 否
已用 IC / 零件： LTC6990，LTC6991，LTC6992-1，LTC6993-2，LTC6994-1
已供物品： 裸板，樣品 IC
LTC6990
21
6990fc
For more information www.linear.com/LTC6990
6990 F17
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1F
R1
R2
RSET
V+
DIV
SET
OUT
GND
OE
C1
R1
R2
V+
RSET
DCB PACKAGE
OE
GND
SET
OUT
V+
DIV
R2
V+
RSET
TSOT-23 PACKAGE
R1
C1
Figure 17. Supply Bypassing and PCB Layout
APPLICATIONS INFORMATION
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6990 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. The most important use issues involve
adequate supply bypassing and proper PCB layout.
Figure 17 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6990. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1F ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but the direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
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