參數(shù)資料
型號(hào): SC16C2552BIA44,518
廠商: NXP Semiconductors
文件頁(yè)數(shù): 10/37頁(yè)
文件大?。?/td> 0K
描述: IC UART DUAL SOT187-2
標(biāo)準(zhǔn)包裝: 500
特點(diǎn): 2 通道
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC
包裝: 帶卷 (TR)
其它名稱: 935274408518
SC16C2552BIA44-T
SC16C2552BIA44-T-ND
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
18 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16.
Modem Control Register bits description
Bit
Symbol
Description
7:5
MCR[7:5]
reserved; initialized to a logic 0
4
MCR[4]
Loopback. Enable the local Loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD and RI
are disconnected from the SC16C2552B I/O pins. Internally the modem
data and control pins are connected into a loopback data conguration
(see Figure 4). In this mode, the receiver and transmitter interrupts remain
fully operational. The modem control interrupts are also operational, but
the interrupts’ sources are switched to the lower four bits of the Modem
Control. Interrupts continue to be controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
3
MCR[3]
OP2. Used to control the modem CD signal in the Loopback mode.
logic 0 = sets OP2 to a logic 1 (normal default condition). In the
Loopback mode, sets CD internally to a logic 1.
logic 1 = sets OP2 to a logic 0. In the Loopback mode, sets CD internally
to a logic 0.
2
MCR[2]
OP1. This bit is used in the Loopback mode only. In the Loopback mode,
this bit is used to write the state of the modem RI interface signal.
1
MCR[1]
RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
0
MCR[0]
DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
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