參數(shù)資料
型號: SC16C650BIN40,112
廠商: NXP Semiconductors
文件頁數(shù): 13/48頁
文件大小: 0K
描述: IC UART SINGLE W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝: 9
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
其它名稱: 568-2045-5
935274389112
SC16C650BIN40
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
20 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
3
(cont.)
Transmit operation in mode ‘1’: When the SC16C650B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0
when FIFO has 1 empty space.
Receive operation in mode ‘1’: When the SC16C650B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a
logic 1 when other FCR bits are written to, or they will not be
programmed.
Table 11.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes)
008
0116
1024
1128
Table 12.
TX FIFO trigger levels
FCR[5]
FCR[4]
TX FIFO trigger level (bytes)
0016
018
1024
1130
Table 10.
FIFO Control Register bits description …continued
Bit
Symbol
Description
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SC16C652B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
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