參數(shù)資料
型號(hào): SC16C650BIN40,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 16/48頁(yè)
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 40-DIP
標(biāo)準(zhǔn)包裝: 9
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
其它名稱: 568-2045-5
935274389112
SC16C650BIN40
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
23 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16.
LCR[5] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
0
no parity
0
1
odd parity
0
1
even parity
1
0
1
force parity ‘1’
1
forced parity ‘0’
Table 17.
LCR[2] stop bit length
LCR[2]
Word length
Stop bit length (bit times)
0
5, 6, 7, 8
1
15
1-1
2
1
6, 7, 8
2
Table 18.
LCR[1:0] word length
LCR[1]
LCR[0]
Word length
005
016
107
118
Table 19.
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
Clock select.
logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16 and
then presented to the programmable Baud Rate Generator (BGR) without
further modication, i.e., divide-by-1 (normal default condition).
logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] equals a
logic 0, is further divided by four (see also Section 6.7 “Programmable baud
6
MCR[6]
IR enable.
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder.
The data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a
logic 0 during idle data conditions.
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