參數(shù)資料
型號(hào): SC16C750BIBS,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 2/44頁(yè)
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 32-HVQFN
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 828 (CN2011-ZH PDF)
其它名稱(chēng): 568-3285
935276388151
SC16C750BIBS-S
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
10 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.2 FIFO operation
The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
6.3 Hardware ow control
When automatic hardware ow control is enabled, the SC16C750B monitors the CTS pin
for a remote buffer overow indication and controls the RTS pin for local buffer overows.
Automatic hardware ow control is selected by setting MCR[5] (RTS) and MCR[1] (CTS)
to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ow control request,
the SC16C750B will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a logic 0,
indicating more data may be sent.
With the auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is emptied. However, under the above described
conditions, the SC16C750B will continue to accept data until the receive FIFO is full.
6.4 Time-out interrupts
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C750B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the receive holding register (RHR) is read.
The actual time-out value is 4 character time.
Table 4.
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS
Assert RTS
16-byte FIFO
11
1
0
44
4
0
88
8
0
14
0
64-byte FIFO
11
1
0
16
0
32
0
56
0
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