參數(shù)資料
型號(hào): SC16C750BIBS,151
廠商: NXP Semiconductors
文件頁數(shù): 5/44頁
文件大小: 0K
描述: IC UART SINGLE W/FIFO 32-HVQFN
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-3285
935276388151
SC16C750BIBS-S
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
13 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.7 Sleep mode
The SC16C750B is designed to operate with low power consumption. A special Sleep
mode is included to further reduce power consumption (the internal oscillator driver is
disabled) when the chip is not being used. With IER[4] enabled (set to a logic 1), the
SC16C750B enters the Sleep mode, but resumes normal operation when a start bit is
detected, a change of state of RX or on any of the modem input pins RI, CTS, DSR, DCD,
or a transmit data is provided by the user. If the Sleep mode is enabled and the
SC16C750B is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after the last character is transmitted or read by the user. In any
case, the Sleep mode will not be entered while an interrupt(s) is pending. The
SC16C750B will stay in the Sleep mode of operation until it is disabled by setting IER[4] to
a logic 0.
6.8 Low power mode
In Low power mode the oscillator is still running and only the clock to the UART core is
cut off. This helps to reduce the operating current to about 1
3. The UART wakes up under
the same conditions as in Sleep mode.
6.9 Loopback mode
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and recongured for loopback internally.
MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the
Loopback mode, OUT1 and OUT2 in the MCR register (bit 2 and bit 3) control the modem
RI and DCD inputs, respectively. MCR signals DTR and RTS (bit 0 and bit 1) are used to
control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the
receiver input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see Figure 6). The CTS, DSR, DCD, and RI are
disconnected from their normal modem control input pins, and instead are connected
internally to RTS, DTR, OUT2 and OUT1. Loopback test data is entered into the Transmit
Holding Register via the user data bus interface, D0 to D7. The transmit UART serializes
the data and passes the serial data to the receive UART via the internal loopback
connection. The receive UART converts the serial data back into parallel data that is then
made available at the user data interface D0 to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
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