參數(shù)資料
型號： SC16C752BIBS,157
廠商： NXP Semiconductors
文件頁數(shù)： 13/47頁
文件大?。?/td> 0K
描述： IC DUAL UART 64BYTE 32HVQFN
標(biāo)準(zhǔn)包裝： 2,450
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-HVQFN（5x5）
包裝： 托盤
其它名稱： 935276389157
SC16C752BIBS
SC16C752BIBS-ND
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
20 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 10 lists and describes the SC16C752B internal registers.
[1]
These registers are accessible only when LCR[7] = logic 0.
[2]
These bits can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
[3]
The Special register set is accessible only when LCR[7] is set to a logic 1.
[4]
Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
Table 10.
SC16C752B internal registers
A2 A1 A0 Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General register set[1]
0
RHR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0
THR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
00
1IER
0/CTS
interrupt
enable[2]
0/RTS
interrupt
enable[2]
0/Xoff[2]
0/X sleep
mode[2]
modem
status
interrupt
receive
line status
interrupt
THR
empty
interrupt
Rx data
available
interrupt
R/W
0
1
0
FCR
RX trigger
level
(MSB)
RX trigger
level (LSB)
0/TX
trigger
level
(MSB)[2]
0/TX
trigger
level
DMA
mode
select
TX FIFO
reset
RX FIFO
reset
FIFO
enable
W
0
1
0
IIR
FCR[0]
0/CTS,
RTS
0/Xoff
interrupt
priority
bit 2
interrupt
priority
bit 1
interrupt
priority
bit 0
interrupt
status
R
01
1LCR
DLAB
break
control bit
set parity
parity type
select
parity
enable
number of
stop bits
word
length
bit 1
word
length
bit 0
R/W
10
0MCR
1
× or
1
× /4
clock[2]
TCR and
TLR
enable[2]
0/Xon
Any[2]
0/enable
loopback
IRQ
enable
OP
FIFO
ready
enable
RTS
DTR
R/W
1
0
1
LSR
0/error in
RX FIFO
THR and
TSR empty
THR
empty
break
interrupt
framing
error
parity
error
overrun
error
data in
receiver
R
11
0MSR
CD
RI
DSR
CTS
ΔCD
ΔRI
ΔDSR
ΔCTS
R
1
SPR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
TCR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
TLR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
11
1FIFO
Rdy
00
RX FIFO
B status
RX FIFO
A status
0
TX FIFO
B status
TX FIFO
A status
R
Special register set[3]
0
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0
1
DLM
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
R/W
Enhanced register set[4]
01
0EFR
auto CTS
auto RTS
Special
character
detect
Enable
IER[7:4],
FCR[5:4],
MCR[7:5]
software
flow
control
bit 3
software
flow
control
bit 2
software
flow
control
bit 1
software
flow
control
bit 0
R/W
1
0
Xon1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
1
Xon2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
Xoff1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
Xoff2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
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