參數(shù)資料
型號: SC16C752IB48,128
廠商: NXP Semiconductors
文件頁數(shù): 43/47頁
文件大?。?/td> 0K
描述: IC DUAL UART 64BYTE 48LQFP
標(biāo)準(zhǔn)包裝: 1
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 568-5955-6
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
5 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CTSA, CTSB
38, 23
I
Clear to Send (Active-LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on the CTS pins indicates the modem or data set is
ready to accept transmit data from the SC16C752. Status can be tested by reading
MSR[4]. These pins only affect the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Feature Register EFR[7] for hardware ow
control operation.
D0-D4,
D5-D7
44-48,
1-3
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least signicant bit and the rst
data bit in a transmit or receive serial data stream.
DSRA, DSRB
39, 20
I
Data Set Ready (Active-LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is
powered-on and is ready for data exchange with the UART. The state of these inputs is
reected in the modem status register (MSR).
DTRA, DTRB
34, 35
O
Data Terminal Ready (Active-LOW). These outputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC16C752
is powered-on and ready. These pins can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the
modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or
after a reset.
GND
17
I
Signal and power ground.
INTA, INTB
30, 29
O
Interrupt A and B (Active-HIGH). These pins provide individual channel interrupts
INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a logic 1, interrupt
sources are enabled in the interrupt enable register (IER). Interrupt conditions include:
receiver errors, available receiver buffer data, available transmit buffer space, or when
a modem status ag is detected. INTA, INTB are in the high-impedance state after
reset.
IOR
19
I
Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on IOR will load
the contents of an internal register dened by address bits A0-A2 onto the SC16C752
data bus (D0-D7) for access by external CPU.
IOW15
I
Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on IOW will
transfer the contents of the data bus (D0-D7) from the external CPU to an internal
register that is dened by address bits A0-A2 and CSA and CSB.
NC
12, 24,
25, 37
-
Not connected.
OPA, OPB
32, 9
O
User dened outputs. This function is associated with individual channels A and B.
The state of these pins is dened by the user through the software settings of MCR[3].
INTA-INTB are set to active mode and OPA-OPB to a logic 0 when MCR[3] is set to a
logic 1. INTA-INTB are set to the 3-State mode and OPA-OPB to a logic 1 when
MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
RESET
36
I
Reset. This pin will reset the internal registers and all the outputs. The UART
transmitter output and the receiver input will be disabled during reset time. RESET is
an active-HIGH input.
RIA, RIB
41, 21
I
Ring Indicator (Active-LOW). These inputs are associated with individual UART
channels, A and B. A logic 0 on these pins indicates the modem has received a ringing
signal from the telephone line. A LOW-to-HIGH transition on these input pins
generates a modem status interrupt, if enabled. The state of these inputs is reected
in the modem status register (MSR).
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
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