參數(shù)資料
型號: SC16C752IB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: Dual UART with 64-byte FIFO
封裝: SC16C752IB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<week 17, 2005,;
文件頁數(shù): 19/47頁
文件大?。?/td> 604K
代理商: SC16C752IB48
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
19 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 10
lists and describes the SC16C752 internal registers.
[1]
[2]
These registers are accessible only when LCR[7] = 0.
The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
Table 10:
Shaded bits are only accessible when EFR[4] is set.
SC16C752 internal registers
A2 A1 A0 Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General Register Set
[1]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
bit 7
bit 7
0/CTS
interrupt
enable
[2]
RX
trigger
level
(MSB)
FCR[0]
bit 6
bit 6
0/RTS
interrupt
enable
[2]
RX trigger
level (LSB)
bit 5
bit 5
0/Xoff
[2]
bit 4
bit 4
0/X sleep
mode
[2]
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
bit 2
bit 2
receive
linestatus
interrupt
TX FIFO
reset
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
R
W
R/W
0
1
0
FCR
0/TX
trigger
level
(MSB)
[2]
0/CTS,
RTS
0/TX
trigger
level
(LSB)
[2]
0/Xoff
W
0
1
0
IIR
FCR[0]
interrupt
priority
bit 2
parity
enable
interrupt
priority
bit 1
numberof
stop bits
interrupt
priority
bit 0
word
length
bit 1
RTS
interrupt
status
R
0
1
1
LCR
DLAB
break
control bit
set parity parity
type
select
0/enable
loop-back
word
length
bit 0
DTR
R/W
1
0
0
MCR
1
×
or
1
×
/4
clock
0/error in
RX FIFO
TCR and
TLR
enable
THR and
TSR
empty
RI
bit 6
bit 6
bit 6
0
0/Xon
Any
IRQ
enable
OP
framing
error
FIFO
ready
enable
parity
error
R/W
1
0
1
LSR
THR
empty
break
interrupt
overrun
error
data in
receiver
R
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
MSR
SPR
TCR
TLR
FIFO
Rdy
CD
bit 7
bit 7
bit 7
0
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
CD
bit 3
bit 3
bit 3
0
RI
bit 2
bit 2
bit 2
0
DSR
bit 1
bit 1
bit 1
TXFIFOB
status
CTS
bit 0
bit 0
bit 0
TX FIFO
A status
R
R/W
R/W
R/W
R
Special Register Set
[3]
0
0
0
0
0
1
Enhanced Register Set
[4]
0
1
0
DLL
DLH
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
R/W
R/W
EFR
Auto
CTS
Auto RTS
Special
character
detect
Enable
enhanced
functions
[2]
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
R/W
1
1
1
1
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
bit 5
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
bit 4
R/W
R/W
R/W
R/W
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