- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372122 > SC16C754 (NXP Semiconductors N.V.) Quad UART with 64-byte FIFO PDF資料下載
參數(shù)資料
| 型號(hào)： | SC16C754 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad UART with 64-byte FIFO |
| 中文描述： | 四UART的64字節(jié)FIFO |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 622K |
| 代理商： | SC16C754 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 04 — 19 June 2003
24 of 49
9397 750 11618
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Line control register (LCR)
This register controls the data communication format. The word length, number of
stop bits, and parity type are selected by writing the appropriate bits to the LCR.
Table 12
shows the line control register bit settings.
Table 12:
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
LCR[6]
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition.
LCR[5]
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
LCR[4]
Parity type select.
Logic 0 = ODD Parity is generated (if LCR[3] = 1).
Logic 1 = EVEN Parity is generated (if LCR[3] = 1).
LCR[3]
Parity enable.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during transmission and the
receiver checks for received parity.
LCR[2]
Number of Stop bits. Specifies the number of stop bits.
0 = 1 stop bit (word length = 5, 6, 7, 8)
1 = 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
00 - 5 bits
01 - 6 bits
10 - 7 bits
11 - 8 bits
6
5
4
3
2
1-0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C754IA68 | Quad UART with 64-byte FIFO |
| SC16C754IB80 | Quad UART with 64-byte FIFO |
| SC2000 | Universal Timeslot Interchange |
| SC2001G-10 | Bus Exchanger |
| SC2001G-13 | Bus Exchanger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C754B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs |
| SC16C754BIA68 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,512 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,518 | 功能描述:UART 接口集成電路 4CH. UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,529 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。