參數(shù)資料
型號： SC16IS760IPW
廠商： NXP Semiconductors N.V.
元件分類： 連接器件
英文描述： Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝： SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù)： 36/62頁
文件大小： 308K
代理商： SC16IS760IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
36 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
9.2 RS-485 RTS output inversion
EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.
When the transmitter has data to be sent it will deasserts the RTS pin (logic 1), and when
the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).
9.3 Auto RS-485
EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of
operation, a ‘master’ station transmits an address character followed by data characters
for the addressed ‘slave’ stations. The slave stations examine the received data and
interrupt the controller if the received character is an address character (parity bit = 1).
To use the auto RS-485 mode the software would have to disable the hardware and
software flow control functions.
9.3.1
Normal multidrop mode
The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).
The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an
address byte is received (parity bit = 1). This address byte will cause the UART to set the
parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at
this time), and at the same time puts this address byte in the RX FIFO. After the controller
examines the byte it must make a decision whether or not to enable the receiver; it should
enable the receiver if the address byte addresses its ID address, and must not enable the
receiver if the address byte does not address its ID address.
If the controller enables the receiver, the receiver will receive the subsequent data until
being disabled by the controller after the controller has received a complete message from
the ‘master’ station. If the controller does not disable the receiver after receiving a
message from the ‘master’ station, the receiver will generate a parity error upon receiving
another address byte. The controller then determines if the address byte addresses its ID
address, if it is not, the controller then can disable the receiver. If the address byte
addresses the ‘slave’ ID address, the controller take no further action, the receiver will
receive the subsequent data.
9.3.2
Auto address detection
If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the
address byte) the receiver will try to detect an address byte that matches the programmed
character in the XOFF2 register. If the received byte is a data byte or an address byte that
does not match the programmed character in the XOFF2 register, the receiver will discard
these data. Upon receiving an address byte that matches the Xoff2 character, the receiver
will be automatically enabled if not already enabled, and the address character is pushed
into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also
generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will
then receive the subsequent data from the ‘master’ station until being disabled by the
controller after having received a message from the ‘master’ station.
If another address byte is received and this address byte does not match Xoff2 character,
the receiver will be automatically disabled and the address byte is ignored. If the address
byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the
parity bit in the parity error bit (LSR bit 2).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC16IS760IPW,112 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE W/IRDA AND GPIO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS760IPW,128 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS760IPW112 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述:
SC16IS760IPW-F 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE W/IRDA AND GPIO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS760IPW-S 功能描述:IC UART I2C/SPI 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標準包裝:250 系列:- 特點:* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND
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