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參數(shù)資料
| 型號(hào)： | SC28C94A1N,112 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 18/39頁(yè) |
| 文件大小： | 0K |
| 描述： | IC UART QUAD W/FIFO 48-DIP |
| 標(biāo)準(zhǔn)包裝： | 7 |
| 特點(diǎn)： | 故障啟動(dòng)位檢測(cè) |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 8 字節(jié) |
| 電源電壓： | 5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 48-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 48-DIP |
| 包裝： | 管件 |
| 其它名稱： | 568-1115-5 935262535112 SC28C94A1N |
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Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
25
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
VCC = 5V ± 10%, TA = –40_C to 85_C, unless otherwise specified.
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
Min
Typ
Max
UNIT
Reset timing
tRES
10
Reset pulse width
200
ns
I/O Port timing
tPS
11
I/O input setup time before RDN Low
0
ns
tPH
11
I/O input hold time after RDN High
0
ns
tPD
11
I/O output valid from
WRN High (WRN or CEN high, whichever occurs first)
RDN Low (RDN or CEN low, whichever occurs last)
40
ns
Interrupt timing
tIR
12
IRQN negated or I/O output High from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Reset command (I/O change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
With respect to a
3.6864MHz clock
on pin X1/CLK
80
ns
Clock timing
tCLK
13
X1/CLK low/high time
125/100
ns
tCLK
13
X1/CLK low/high time (above 4MHz; X1/CLK
÷ 2 active)
56/56
ns
tCLK5
13
X1/CLK frequency
0
3.6864
8.0
MHz
tCTC
13
Counter/timer clock high or low time
60
ns
fCTC5
13
Counter/timer clock frequency
0
8
MHz
tRX
13
RxC high or low time
30
ns
fRX5
13
RxC frequency (16X)
RxC frequency (1X)
0
16
1.0
MHz
tTX
13
TxC high or low time
30
ns
fTX5
13
TxC frequency (16X)
TxC frequency (1X)
0
16
1.0
MHz
Transmitter timing
tTXD
14
TxD output delay from TxC low
70
ns
tTCS
14
TxC output delay from TxD output data
–10
+10
ns
Receiver timing
tRXS
15
RxD data setup time to RxC high
60
5
ns
tRXH
15
RxD data hold time from RxC high
60
5
ns
NOTES:
1. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of VIL and VIH,
as appropriate.
2. Typical values are at +25
°C, typical supply voltages, and typical processing parameters.
3. Test condition for interrupt and I/O outputs: CL = 50 pF, RL = 2.7 k to VCC. Test conditions for rest of outputs: CL = 150 pF.
4. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
5. The minimum value is not tested, but is guaranteed by design. For tCLK minimum test rate is 2.0 MHz.
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