參數(shù)資料
型號： SC28C94A1N,112
廠商： NXP Semiconductors
文件頁數(shù)： 6/39頁
文件大?。?/td> 0K
描述： IC UART QUAD W/FIFO 48-DIP
標(biāo)準(zhǔn)包裝： 7
特點： 故障啟動位檢測
通道數(shù)： 4，QUART
FIFO's： 8 字節(jié)
電源電壓： 5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 48-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 48-DIP
包裝： 管件
其它名稱： 568-1115-5
935262535112
SC28C94A1N
Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
14
Table 4.
Register Bit Formats, Duart ab. [duplicated for Duart cd] (continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SR (Status Register)
Rec’d. Break
Framing Error
Parity Error
Overrun Error
TxEMT
TxRDY
RxFULL
RxRDY
0 = No
1 = Yes
*
0 = No
1 = Yes
*
0 = No
1 = Yes
*
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE: These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these
bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. Unless reset with the ‘Error
Reset’ (CR command 40) or receiver reset, these bits will remain active in the Status Register after the RxFIFO is empty. In block error mode,
block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
ACR (Auxiliary Control Register)
BRG Set
Select
Counter/Timer
Mode and Source
Delta
I/O1b
Delta
I/O0b
Delta
I/O1a
Delta
I/O0a
0 = set 1
1 = set 2
See text
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
ISR (Interrupt Status Register)
I/O Port
Change
Delta
BREAKb
RxRDY/
FFULLb
TxRDYb
Counter
Ready
Delta
BREAKa
RxRDY/
FFULLa
TxRDYa
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
IMR (Interrupt Mask Register)
I/O Port
Change
INT
Delta
BREAKb
INT
RxRDY/
FFULLb
INT
TxRDYb
INT
Counter
Ready
INT
Delta
BREAKa
INT
RxRDY/
FFULLa
INT
TxRDYa
INT
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
CTUR (Counter/Timer Upper Register)
C/T[15]
C/T[14]
C/T[13]
C/T[12]
C/T[11]
C/T[10]
C/T[9]
C/T[8]
CTUR (Counter/Timer Lower Register)
C/T[7]
C/T[6]
C/T[5]
C/T[4]
C/T[3]
C/T[2]
C/T[1]
C/T[0]
IPR (Input Port Register)
I/O3b
I/O2b
I/O3a
I/O2a
I/O1b
I/O0b
I/O1a
I/O0a
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
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