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參數(shù)資料
| 型號(hào)： | SC80C32XXX-36SV |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, SIDE BRAZED, DIP-40 |
| 文件頁(yè)數(shù)： | 106/109頁(yè) |
| 文件大?。?/td> | 10824K |
| 代理商： | SC80C32XXX-36SV |
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808
32117D–AVR-01/12
AT32UC3C
The Master Clock (IMCK) frequency is 8*(NBCHAN+1)*(IMCKFS+1) times the sample fre-
quency (fs), i.e. IWS frequency. The Serial Clock (ISCK) frequency is (NBCHAN+1)*Slot Length
times the sample frequency (fs), where Slot Length is defined in
Warning: MR.IMCKMODE should only be written as one if the Master Clock frequency is strictly
higher than the Serial Clock.
If a Master Clock output is not required, the GCLK_IISC generic clock is used as ISCK, by writ-
ing a zero to MR.IMCKMODE. Alternatively, if the frequency of the generic clock used is a
multiple of the required ISCK frequency, the IMCK to ISCK divider can be used with the ratio
defined by writing the MR.IMCKFS field.
The IWS pin is used as Word Select in I2S format and as Frame Synchronization in TDM format,
as described in Section 30.6.4 and Section 30.6.5 respectively.
Table 30-2.
Slot Length
MR.DATALENGTH
Word Length
Slot Length
0
32 bits
32
1
24 bits
32 if MR.IWS24 is zero
24 if MR.IWS24 is one
2
20 bits
3
18 bits
4
16 bits
16
5
16 bits compact stereo
6
8 bits
8
7
8 bits compact stereo
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