參數(shù)資料
型號(hào)： SCM69C433
廠商： Motorola, Inc.
英文描述： A Flexible Content-Addressable Memory (16K x 64 CAM)(1M內(nèi)容可尋址存儲(chǔ)器)
中文描述： 一個(gè)靈活的內(nèi)容尋址存儲(chǔ)器（16K的× 64 CAM）的（100萬內(nèi)容可尋址存儲(chǔ)器）
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 167K
代理商： SCM69C433
MCM69C433
SCM69C433
3
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
42 – 44
A2 – A0
Input
3–bit control port address bus.
58
DTACK
Output
Control port data transfer acknowledge (Open Drain).
17 – 20, 23 – 26,
29 – 32, 35 – 38
DQ15 – DQ0
I/O
16–bit bidirectional control port data bus.
61
G
Input
Output Enable control of MQ31 – MQ0.
57
IRQ
Output
Control port interrupt (Open Drain).
39
K
Input
Interface Clock, max frequency of 66 MHz.
47
KMODE
Input
See Note.
89
LH/SM
Input
Latch High/Start Match. Initiates match sequence on match data present on
MQ31 – MQ0.
92
LL
Input
Latch Low. Latches low order bits if match width is > 32 bits.
64
MC
Output
Match Complete (Open Drain).
67 – 70, 73 – 76,
79 – 82, 85 – 88,
93 – 96, 99, 100,
1, 2, 5 – 8, 11 – 14
MQ31 – MQ0
I/O
32–bit common I/O CAM data. Used for input of match RAM and data RAM
values.
62
MS
Output
Match Successful (Open Drain).
56
RESET
Input
Resets chip to a known state.
46
SEL
Input
Control port chip select, active low.
52
TCK
Input
Test Clock, part of JTAG interface.
50
TDI
Input
Test Data In, part of JTAG interface.
55
TDO
Output
Test Data Out, part of JTAG interface.
51
TMS
Input
Test Mode Select, part of JTAG interface.
49
TRST
Input
Tap Reset part of JTAG interface.
63
VPC
Output
Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has
occurred (Open Drain).
45
WE
Input
Control port Write Enable.
4, 10, 16, 22, 27, 33,
41, 48, 54, 59, 65, 71,
77, 84, 91, 97
VDD
Supply
Power Supply: 3.3 V
±
5%.
3, 9, 15, 21, 28, 34,
40, 53, 60, 66, 72,
78, 83, 90, 98
VSS
Supply
Ground.
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
K
RESET
KMODE
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