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參數(shù)資料
| 型號： | SE5537FE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Sample-and-hold amplifier |
| 中文描述： | SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 103K |
| 代理商： | SE5537FE |
Philips Semiconductors Linear Products
Product specification
NE/SE5537
Sample-and-hold amplifier
884
August 31, 1994
853-1044 13721
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2k
load. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
FEATURES
Operates from
±
5V to
±
18V supplies
Hold leakage current 6pA @ T
J
= 25
°
C
Less than 4
μ
s acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01
μ
F
Low input offset: 1MV (typical)
0.002% gain accuracy with R
L
=2k
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
PIN CONFIGURATIONS
FE and N Packages
D
1
Package
NOTE:
1. SO and non-standard pinouts.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
14
13
12
11
10
9
V+
OFFSET ADJUST
INPUT
V–
NC
LOGIC
LOGIC REFERENCE
OUTPUT
C
h
V–
INPUT
OUTPUT
NC
NC
V+
LOGIC REFERENCE
NC
C
h
NC
V
OS
ADJ
NC
LOGIC
BLOCK DIAGRAM
OFFSET
OUTPUT
INPUT
LOGIC
LOGIC
REFERENCE
HOLD
300
30k
2
3
8
7
6
5
–
+
–
+
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
0 to +70
°
C
0 to +70
°
C
-55
°
C to +125
°
C
ORDER CODE
DWG #
8-Pin Plastic Dual In-Line Package (DIP)
NE5537N
0404B
14-Pin Plastic Small Outline (SO) Package
NE5537D
0175D
8-Pin Plastic Dual In-Line Package (DIP)
SE5537FE
0404B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SE5539N | High frequency operational amplifier |
| SE5539 | High frequency operational amplifier |
| SE5539F | High frequency operational amplifier |
| SE5560 | Switched-mode power supply control circuit |
| SE5560F | Switched-mode power supply control circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SE5539 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High frequency operational amplifier |
| SE5539F | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High frequency operational amplifier |
| SE5539N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High frequency operational amplifier |
| SE555 | 制造商:NEC 制造商全稱:NEC 功能描述:PRECISION TIMERS |
| SE555C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PRECISION TIMERS SE555C FROM TI IS NOT RECOMMENDED FOR NEW DESIGNS |
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