參數(shù)資料
型號: SE5537FE
廠商: NXP SEMICONDUCTORS
元件分類: 運動控制電子
英文描述: Sample-and-hold amplifier
中文描述: SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, PDIP8
封裝: 0.300 INCH, PLASTIC, DIP-8
文件頁數(shù): 3/8頁
文件大?。?/td> 103K
代理商: SE5537FE
Philips Semiconductors Linear Products
Product specification
NE/SE5537
Sample-and-hold amplifier
August 31, 1994
886
DC ELECTRICAL CHARACTERISTICS
1
SYMBOL
PARAMETER
TEST CONDITIONS
SE5537
Typ
1
NE5537
Typ
2
UNIT
Min
Max
3
Min
Max
7
T
J
=25
°
C
mV
V
OS
Input offset voltage
4
Full temperature range
T
J
=25
°
C
5
25
10
50
mV
nA
5
10
I
BIAS
Input bias current
4
Full temperature range
T
J
=25
°
C
T
J
=25
°
C
-10V
V
IN
10V, R
L
=2k
-11.5V
V
IN
11.5V,
R
L
=10k
Full temperature range
75
100
nA
%
Input impedance
Gain error
10
10
0.002
10
10
0.004
0.007
0.01
0.02
0.02
%
Feedthrough attenuation
ratio at 1kHz
Output impedance
T
J
=25
°
C, C
H
=0.01
μ
F
86
96
80
90
dB
T
J
=25
°
C, “HOLD” mode
Full temperature range
T
J
=25
°
C, C
H
=0.01
μ
F, V
OUT
=0
T
J
=25
°
C
0.5
2
4
0.5
4
6
“HOLD” Step
2
Supply current
4
Logic and logic reference
input current
Leakage current into hold
capacitor
4
0.5
4.5
2.0
6.5
1.0
4.5
2.5
7.5
mV
mA
I
CC
T
J
=25
°
C
2
10
2
10
μ
A
T
J
=25
°
C “hold” mode
3
6
50
6
100
pA
Acquisition time to 0.1%
V
OUT
=10V,
C
H
=1000pF
C
H
=0.01
μ
F
4
4
μ
s
20
20
μ
s
Hold capacitor charging
current
Supply voltage rejection
ratio
Differential logic threshold
V
IN
-V
OUT
=2V
5
5
mA
SVRR
V
OUT
=0V
80
110
80
110
dB
T
J
=25
°
C
0.8
1.4
2.4
0.8
1.4
2.4
V
NOTES:
1. Unless otherwise specified, the following conditions apply: Unit is in “sample” mode. V
S
=
±
15V, T
J
=25
°
C, -11.5V
V
IN
11.5V, C
H
=0.01
μ
F, and
R
=2k
. Logic reference voltage=0V and logic voltage=2.5V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor
value.
3. Leakage current is measured at a junction temperature of 25
°
C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25
°
C value for each 11
°
C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. These parameters guaranteed over a supply voltage range of
±
5 to
±
18V.
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