(VDD
參數(shù)資料
型號： SI3220DCX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 13/112頁
文件大?。?/td> 0K
描述： DAUGHTER CARD W/DISCRETE INTRFC
標準包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3220
已供物品： 板，CD
Si3220/25 Si3200/02
Rev. 1.3
11
Not
Recommended
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Table 5. AC Characteristics
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
Overload Level
2.5
—
VPK
Overload Compression
2-Wire – PCM
—
Single Frequency Distortion1
2-Wire – PCM or PCM – 2-Wire:
200Hz to 3.4kHz
—
–85
–65
dB
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
—
–87
–65
dB
Signal-to-(Noise + Distortion)
Ratio2
200Hz to 3.4kHz
D/A or A/D 8-bit
Active off-hook, and OHT, any ZT
—
Audio Tone Generator Signal-to-
Distortion Ratio2
0 dBm0, Active off-hook, and
OHT, any ZT
46
—
dB
Intermodulation Distortion
—
–41
dB
Gain Accuracy2
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
–0.25
—
+0.25
dB
Attenuation Distortion vs. Freq.
0 dBm 0
—
Group Delay vs. Frequency
—
Gain Tracking3
1014 Hz sine wave,
reference level –10 dBm
Signal level:
——
—
3 dB to –37 dB
—
± 0.25
dB
–37 dB to –50 dB
—
± 0.5
dB
–50 dB to –60 dB
—
± 1.0
dB
Round-Trip Group Delay
1014 Hz, Within same time-slot
—
600
700
s
Crosstalk between Channels
TX or RX to TX
TX or RX to RX
0dBm0,
300Hz to 3.4kHz
—
–108
–75
dB
Gain Step Increment4
Step size around 0 dB
—
±0.0005
—
dB
2-Wire Return Loss5
200Hz to 3.4kHz
26
30
—
dB
Transhybrid Balance5
300Hz to 3.4kHz
34
40
—
dB
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –
to +6 dB. The step size in dB varies over the
5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 , ZS = 600 synthesized using RS register
coefficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
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相關代理商/技術參數(shù)
參數(shù)描述
SI3220-F-GQ 制造商:Silicon Laboratories Inc 功能描述:DUAL-CHANNEL SLIC/CODEC WITH INTERNAL 65 VRMS BALANCED RINGI - Trays
SI3220-F-GQR 制造商:Silicon Laboratories Inc 功能描述:DUAL-CHANNEL SLIC/CODEC WITH INTERNAL 65 VRMS BALANCED RINGI - Tape and Reel
Si3220-FQ 功能描述:電信線路管理 IC Dual-Channel SLIC/ codec RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3220-FQR 制造商:Silicon Laboratories Inc 功能描述: 制造商:Silicon Laboratories Inc 功能描述:SLIC 2CH 63DB 45MA 3.3V/5V 64TQFP - Tape and Reel
Si3220-G-FQ 功能描述:電信線路管理 IC Dual-Channel SLIC codec RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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