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參數(shù)資料
| 型號(hào)： | SI3220DCX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 96/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/DISCRETE INTRFC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3220 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
84
Rev. 1.3
Not
Recommended
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3.31. General Circuit Interface
The Dual ProSLIC devices also contain an alternate
communication interface to the SPI and PCM control
and data interface. The general circuit interface (GCI) is
used for the transmission and reception of both control
and data information onto a GCI bus. The PCM and GCI
interfaces are both four-wire interfaces and share the
same pins. The SPI control interface is not used as a
communication interface in the GCI mode but rather as
hard-wired
channel
selector
pins.
The
selection
between PCM and GCI modes is performed out of reset
to select the communication mode and how the pins are
used in each mode.
If GCI mode is selected, the following pins must be tied
to the correct state to select one of eight subframe
timeslots in the GCI frame (described below). These
pins must remain in this state while the Dual ProSLIC is
operating. Selecting a particular subframe causes that
individual Dual ProSLIC device to transmit and receive
on the appropriate subframe in the GCI frame, which is
initiated by an FSYNC pulse. No further register settings
are needed to select which subframe a device uses,
and the subframe for a particular device cannot be
changed while in operation.
In GCI mode, the PCLK input requires either a
2.048 MHz or a 4.096 MHz clock signal, and the
FSYNC input requires an 8 kHz frame sync signal. The
overall unit of data used to communicate on the GCI
highway is a frame 125 s in length. Each frame is
initiated by a pulse on the FSYNC pin whose rising
edge signifies the beginning of the next frame. In 2x
PCLK mode, the user sees twice as many PCLK cycles
during each 125 s frame versus 1x PCLK mode. Each
frame consists of eight fixed timeslot subframes that are
assigned by the subframe select pins as described
above (SDI, SDO, and CS). Within each subframe are
four channels (bytes) of data including two voice data
channels, B1 and B2, one Monitor channel, M, used for
initialization and setup of the device, and one Signaling
and Control channel, SC, used for communicating the
status of the device and initiating commands. Within the
SC channel are six Command/Indicate (C/I) bits and two
Table 45. PCM or GCI Mode Selection
SDITHRU SCLK
Mode Selected
0
GCI Mode—1x PCLK (2.048 MHz)
0
1
GCI Mode—2x PCLK (4.096 MHz)
1
x
PCM Mode
Note:
Values shown are the states of the pins at the rising
edge of RESET.
Table 46. Pin Functionality in PCM or GCI Mode
Pin Name
PCM Mode
GCI Mode
CS
SPI Chip Select
Channel Selector,
bit 0
SCLK
SPI Clock Input
PCLK Rate
Selector
SDI
SPI Serial Data Input
Channel Selector,
bit 2
SDO
SPI Serial Data
Output
Channel Selector,
bit 1
SDITHRU
SPI Data Throughput
pin for Daisy Chaining
Operation (Connects
to the SDI pin of the
subsequent device in
the daisy chain)
PCM/GCI Mode
Selector
FSYNC
PCM Frame Sync
Input
GCI Frame Sync
Input
PCLK
PCM Input Clock
GCI Input Clock
DTX
PCM Data Transmit
GCI Data Transmit
DRX
PCM Data Receive
GCI Data Receive
Note:
This table denotes pin functionality after the rising
edge of RESET and mode selection.
Table 47. GCI Mode Subframe Selection
SDI
SDO
CS
GCI Subframe 0 Selected
(Voice channels 1–2)
11
1
GCI Subframe 1 Selected
(Voice channels 3–4)
11
0
GCI Subframe 2 Selected
(Voice channels 5–6)
10
1
GCI Subframe 3 Selected
(Voice channels 7–8)
10
0
GCI Subframe 4 Selected
(Voice channels 9–10)
01
1
GCI Subframe 5 Selected
(Voice channels 11–12)
01
0
GCI Subframe 6 Selected
(Voice channels 13–14)
00
1
GCI Subframe 7 Selected
(Voice channels 15–16)
00
0
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